Scribe Line Memory Array Test Apparatus for Minimal Voltage Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
It is challenging to test and measure the performance of semiconductor IC devices during the fabrication process, especially for memory arrays like SRAM, as it is not practical to add pinouts or routing for accessing electrical components in the scribe lines, limiting the monitoring of basic electrical characteristics and operational parameters such as minimal operating voltage.
Innovation Solution
A test apparatus is disposed in the scribe line between semiconductor IC devices, featuring a built-in self-test circuit and a memory array duplication, which includes test pads, a voltage divider, and a counter to perform minimal operating voltage detection by dividing the voltage range into multiple testing voltages and conducting write, read, and compare operations to determine the minimal operating voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a test apparatus is disposed in the scribe line to enable memory array testing during fabrication, then measurement capability is improved, but device complexity increases
Solution Approach 1:
The patent creates a duplicate memory array structure within the test apparatus located in the scribe line. This copied memory array (comprising word lines, bit lines, and memory cells) mirrors the actual memory array structure, enabling independent testing without modifying the original device. The copy allows full performance characterization while keeping the production devices unchanged.
Solution Approach 2:
The test apparatus acts as an intermediary system between the fabrication process and the final packaged product. By placing the test circuitry in the scribe line area, the patent enables intermediate testing during manufacturing, bridging the gap between fabrication and final package testing without requiring additional pinouts or routing on the actual IC devices.
2Measurement precision
If additional pinouts or routing are added to access electrical components for testing, then measurement capability is improved, but manufacturing ease deteriorates
Solution Approach 1:
The scribe line area, traditionally used only for separation and basic process monitoring, is repurposed to host a complete test apparatus with memory array duplication and testing circuitry. This multi-functional use of the scribe line enables comprehensive electrical characteristic monitoring without adding dedicated test structures to each IC device, maintaining manufacturing simplicity.
Solution Approach 2:
Instead of adding access routing to each individual IC device, the patent creates a copied memory array structure in the scribe line that can be tested independently. This copying approach allows full electrical characteristic monitoring capability without modifying the original IC device layout or adding complex routing.
3Measurement precision
If voltage range is divided into multiple testing voltages for minimal operating voltage detection, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The voltage range is segmented into multiple discrete testing voltages (e.g., 0.7V, 0.75V, 0.8V, 0.85V, 0.9V) to systematically determine the minimal operating voltage. This segmentation allows precise identification of the threshold voltage where the memory array transitions from non-functional to functional, improving measurement accuracy while maintaining a manageable testing sequence.
Data Source
AI summary
The disclosure is related a method for testing and measuring the performances of electrical components on a semiconductor IC device through a test apparatus (also referred to as a testline) disposed in a scribe line between the semiconductor IC devices on a wafer. The test apparatus may include a built-in self-test (BIST) circuit and a duplication of the electrical components subjected to the performance measurement. Minimum and maximum testing voltages are provided to the test apparatus, where the range of voltage between the minimum and maximum testing voltages are divided into a plurality of testing operational voltages which are applied to the test apparatus. For each testing operational voltages, a memory array operation test is performed, where at least one of the testing operational voltages resulting in a performance failure is identified as the minimal operating voltage of the memory array.