Scribe Line Probing Pad Layout for Smaller Memory Chip Edges
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Solution Overview
Problem
The design of LPDDR4 memory chips with circuit probing pads and bonding pads near the edge increases the size and cost due to the significant area occupied by these pads, which is not efficiently managed in existing semiconductor technologies.
Innovation Solution
A scribe line structure is introduced where the die region is surrounded by a scribe line region, with circuit probing pads placed on both the die region and the scribe line region, allowing for efficient testing and reduction in chip size by strategically positioning pads to minimize area usage during the dicing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If circuit probing pads and bonding pads are located near the edge of the memory chip to improve high-speed electrical characteristics, then electrical performance is improved, but the area occupied by these pads increases, resulting in higher cost and larger chip size
Solution Approach 1:
The patent extends the utilization of the scribe line region from a traditional linear path into a two-dimensional area that can accommodate circuit probing pads. By placing pads on both the die region and the scribe line region, the design effectively uses the vertical dimension (width of scribe line) to reduce the horizontal footprint on the die, thereby improving electrical characteristics while minimizing area occupation.
Solution Approach 2:
The patent recovers the scribe line region, which is typically discarded or used only for separation, and transforms it into a functional area for hosting circuit probing pads. This recovery of previously wasted space allows pads to be positioned optimally for electrical performance without increasing the die area, as the pads on the scribe line region can be partially removed during dicing.
2Ease of operation
If circuit probing pads are placed on the die region to enable testing, then testing functionality is achieved, but the area occupied by pads increases, resulting in larger chip size
Solution Approach 1:
The scribe line region is given multiple functions: it serves both as the traditional separation line for dicing and as a host for circuit probing pads for testing. This multi-functionality allows the same physical space to fulfill multiple roles, enabling testing functionality without dedicating additional area on the die region, thus maintaining compact chip size.
Solution Approach 2:
The patent utilizes the width of the scribe line region (vertical dimension) to place circuit probing pads, rather than only using the horizontal dimension on the die region. This dimensional shift allows testing pads to be positioned in the scribe line area, reducing the area consumption on the functional die while maintaining full testing capability.
Data Source
AI summary
A scribe line structure is provided. The scribe line structure includes a die region, a scribe line region, and one or more circuit probing pads. The die region is disposed on a semiconductor wafer. The scribe line region surrounds the die region. The one or more circuit probing pads are disposed on a first top surface of the die region and a second top surface of the scribe line region.