Scribe Line Probing Pad Layout for Smaller Memory Chip Area
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Solution Overview
Problem
The area occupied by probing and bonding pads in semiconductor chips is significant, leading to increased cost and size, which is a challenge in designing LPDDR4 memory chips.
Innovation Solution
A scribe line structure is introduced with circuit probing pads on both the die region and scribe line region, allowing for testing and reducing the overall area by incorporating pads on both surfaces and minimizing their impact on the die region's size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If circuit probing pads are located near the edge of the memory chip, then high-speed electrical characteristics are improved, but the area occupied by probing pads and bonding pads increases, resulting in higher cost and larger size
Solution Approach 1:
The patent extends probing pads from a single surface to both top surfaces of the scribe line region, utilizing the third dimension (depth/layering) to distribute pad areas. This dimensional transition allows the probing function to be achieved across multiple surfaces while reducing the footprint on any single surface, thereby maintaining electrical performance without proportionally increasing total chip area.
Solution Approach 2:
The scribe line region is transformed into a multi-functional structure that serves both as a separation region between dies and as a carrier for circuit probing pads. By placing pads on both top surfaces of the scribe line region, the structure simultaneously provides mechanical support, electrical testing capability, and area optimization, reducing the need for dedicated pad areas within the die region itself.
2Productivity
If there are hundreds or thousands of memory chips on a semiconductor wafer, then productivity is improved, but the area occupied by probing pads and bonding pads on each chip accumulates, resulting in higher overall cost
Solution Approach 1:
The patent merges the probing pad function with the scribe line structure, combining what were previously separate elements (probing pads and scribe lines) into an integrated structure. This merging allows the probing pads to be positioned in the scribe line region, sharing the same physical space and reducing the cumulative pad area across multiple chips on a wafer, thereby lowering overall manufacturing cost while maintaining high productivity.
3Reliability
If probing pads are placed on the die region, then testing capability is improved, but the die region's area is reduced, resulting in smaller chip size
Solution Approach 1:
The patent extracts the probing pad function from the die region and relocates it to the scribe line region. This extraction separates the testing function from the active circuit area, allowing the die region to maintain its full area for functional circuits while the scribe line region provides the necessary probing access. The dual-surface configuration ensures comprehensive testing capability without encroaching on die area.
Data Source
AI summary
A scribe line structure is provided. The scribe line structure includes a die region, a scribe line region, and one or more circuit probing pads. The die region is disposed on a semiconductor wafer. The scribe line region surrounds the die region. The one or more circuit probing pads are disposed on a first top surface of the die region and a second top surface of the scribe line region.