Scribe Line Probing Pad Layout for Smaller Flip-Chip Memory Dies
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Solution Overview
Problem
The high data rate of LPDDR5 memory chips exceeds the capabilities of standard wire bonding BGA packages, leading to increased costs and larger chip sizes due to the significant area occupied by circuit probing pads, which are larger than copper pillars used in flip-chip packages.
Innovation Solution
A scribe line structure is introduced, featuring die regions surrounded by a scribe line region, with bump pads and metal wires connecting circuit probing pads on the scribe line region to bump pads on the die region, allowing for efficient electrical connection and reducing the overall chip size by minimizing the area occupied by probing pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If circuit probing pads are placed near the edge of the memory chip to improve high-speed electrical characteristics, then electrical performance is improved, but the area occupied by probing pads increases significantly
Solution Approach 1:
The patent utilizes the scribe line region, which is typically a wasted peripheral area during wafer fabrication, to accommodate circuit probing pads. By moving probing pads from the main die area to the scribe line region, the design effectively uses a different spatial dimension (the peripheral scribe line area) that would otherwise be non-functional, thereby reducing the probing pad area impact on the active chip area while maintaining electrical connection capabilities.
Solution Approach 2:
The patent introduces metal wires as intermediaries to connect bump pads on the die region to circuit probing pads on the scribe line region. This intermediary connection structure allows the probing pads to be positioned in the scribe line region away from the main die area, reducing the area occupation on the active chip while maintaining electrical connectivity through the metal wire mediation.
2Area of stationary object
If the area of probing pads is reduced to minimize chip size, then chip area is reduced, but electrical connectivity may be compromised
Solution Approach 1:
The patent extends the electrical connection path into the scribe line region, utilizing the peripheral area for probing pad placement. This dimensional relocation allows smaller probing pads on the main die to connect to adequately sized probing pads in the scribe line region through metal wires, maintaining electrical connectivity while reducing the area impact on the active chip region.
Solution Approach 2:
Metal wires serve as intermediaries to bridge the bump pads on the die region and the circuit probing pads on the scribe line region. This intermediary connection ensures reliable electrical connectivity between the functional die area and the probing pads located in the peripheral scribe line region, maintaining signal integrity despite the spatial separation and area reduction.
Data Source
AI summary
A scribe line structure is provided. The scribe line structure includes a die region, a scribe line region, one or more bump pads, one or more circuit probing pads, and one or more metal wires. The die region is disposed on a semiconductor wafer. The scribe line region surrounds the die region. The one or more bump pads are disposed on a first top surface of an edge region of the die region. The one or more circuit probing pads are disposed on a second top surface of the scribe line region. The one or more metal wires are disposed on the first top surface of the die region and the second top surface of the scribe line region, and configured to electrically connect the one or more bump pads to the one or more circuit probing pads.