Scribe Line Test Pattern Layout for Photolithography Margin
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Solution Overview
Problem
Semiconductor devices face challenges in maximizing the use of scribe line space and increasing the number of chip regions, as well as enhancing the process margin of photolithography, due to the limited area available for forming key patterns and test elements.
Innovation Solution
The semiconductor device incorporates a test element group with key patterns disposed below pads on the scribe line, allowing vertical overlap and efficient use of the limited space, thereby increasing the number of chip regions and improving photolithography process margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If key patterns and test elements are formed on the scribe line, then photolithography process margin is improved, but scribe line space utilization deteriorates
Solution Approach 1:
The patent applies dimensionality change by forming key patterns at different vertical levels (depths) within the scribe line. Specifically, first key patterns are formed at a first level and second key patterns are formed at a second level different from the first level, allowing both sets of patterns to coexist in the same horizontal footprint area. This vertical stacking approach resolves the contradiction by utilizing the third dimension (depth) to increase space utilization while maintaining adequate spacing for photolithography process margin.
2Productivity
If more chip regions are integrated on the substrate, then productivity is improved, but scribe line area availability deteriorates
Solution Approach 1:
By forming key patterns at different vertical levels in the scribe line, the patent effectively increases the capacity of the scribe line to accommodate additional features. This vertical arrangement frees up horizontal space that can be used to increase the number of chip regions on the substrate, thereby improving productivity without sacrificing scribe line functionality.
Solution Approach 2:
The patent segments the scribe line into multiple vertical levels, with different key patterns formed at different depths. This segmentation allows independent optimization of each level's patterns and enables more efficient use of the scribe line space, contributing to increased chip region integration.
Data Source
AI summary
Disclosed is a semiconductor device comprising a substrate, a first lower pattern group on the substrate and including a first key pattern and first lower test patterns horizontally spaced apart from the first key pattern, and a first upper pattern group on the first lower pattern group and including first pads horizontally spaced apart from each other and first upper test patterns between adjacent ones of the first pads. The first key pattern is configured to be used for a photography process associated with fabrication of the semiconductor device. The first pads are electrically connected to the first upper test patterns. One of the first pads vertically overlaps with the first key pattern.