Scribe Line Test Modules With Copied Matched Device Layouts
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Solution Overview
Problem
Conventional scribe line test modules (TMs) do not provide a complete or accurate assessment of circuit performance, particularly for analog ICs and mixed signal ICs, due to lacking important subcircuit matching aspects, leading to delayed detection of process-design-layout interactions that can cause delivery disruptions and wafer scrap.
Innovation Solution
The implementation of subcircuit-based TMs that copy the matching layout aspects of matched devices in the matched component portions of the IC die, including structure, layers, shapes, sizes, and separation distances, to accurately assess the performance of IC die and identify process-design-layout interactions specific to particular IC designs, without requiring specific probe card hardware for each IC design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional scribe line test modules are used, then testing can be performed with generic probe systems, but the assessment of circuit performance is incomplete and inaccurate
Solution Approach 1:
The test module copies the matching layout aspects of matched devices from the IC die, including structure, layers, shapes, sizes, and separation distances. This copying approach enables accurate assessment of circuit performance while maintaining a standardized test module structure that can be used across different IC designs.
2Reliability
If wafer level testing is implemented, then delivery disruptions can be prevented, but testing costs increase significantly
Solution Approach 1:
The test module is designed with universal applicability across different IC designs by using standardized probe card interfaces and generic probe systems. The matching layout aspects are copied into the test module structure, allowing a single test module design to serve multiple IC designs, thereby reducing per-wafer testing costs while maintaining delivery reliability.
3Measurement precision
If specific probe card hardware is designed for each IC design, then accurate testing can be achieved, but device complexity and cost increase
Solution Approach 1:
Instead of designing specific probe card hardware for each IC design, the matching layout aspects of matched devices are copied into the test module structure. This allows accurate performance assessment to be achieved through the copied layout geometry rather than through custom probe card designs, thereby maintaining test system versatility across different IC designs.
Data Source
AI summary
A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at least one matched component portion that includes at least two matched devices. The first subcircuit is arranged in a layout on the IC die. A plurality of scribe line areas having a scribe line width dimension are interposed between the plurality of IC die areas. At least one subcircuit-based test module (TM) is positioned within the scribe line areas, wherein the subcircuit-based TMs implement a schematic for the first subcircuit with a TM layout that copies the layout on the IC die for at least the two matched devices in the matched component portion and alters the layout on the IC die for a portion of the first subcircuit other than the matched devices in matched component portion to fit the TM layout of the first subcircuit within the scribe line width dimension.