Scribe-Area Passivation Recesses for Void-Resistant Wafer Bonding
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Solution Overview
Problem
During semiconductor wafer bonding, contaminants can be trapped at the bond line, creating voids that reduce bond strength and can render semiconductor devices inoperable.
Innovation Solution
A semiconductor wafer with a passivation layer featuring recessed portions at the scribe area between dies, which captures contaminants and prevents them from forming voids at the bonding interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer bonding is performed with standard flat surfaces, then the bonding process is simple and fast, but contaminants are trapped at the bond line creating voids that reduce bond strength
Solution Approach 1:
The patent introduces recessed portions at specific locations (scribe areas) of the wafer bonding surface, creating local variations in surface topology. These recessed portions have different geometric properties compared to the surrounding flat bonding surface, allowing contaminants to be trapped in designated areas rather than compromising the overall bond strength. This local modification approach maintains simplicity in most areas while addressing contamination issues at critical locations.
Solution Approach 2:
The recessed portions act as intermediary structures that mediate between the bonding surface and contaminants. Instead of allowing contaminants to directly compromise the bond line, the recessed portions serve as intermediate trapping zones that capture and isolate contaminants, preventing them from interfering with the actual bonding interface between wafers.
2Manufacturing precision
If recessed portions are added to the passivation layer, then contaminant trapping is improved and void formation is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The recessed portions are formed in the passivation layer before the wafer bonding process occurs. This preliminary structuring of the passivation layer with pre-defined contaminant trapping zones allows the bonding process to proceed without modification, while the pre-formed recesses automatically capture contaminants as they migrate to the bonding interface during the bonding process.
Solution Approach 2:
The passivation layer is modified locally at scribe areas to create recessed portions, rather than changing the entire passivation layer structure. This localized modification approach minimizes the impact on overall manufacturing complexity while providing the necessary contaminant trapping functionality at critical locations where void formation is most problematic.
3Productivity
If contaminants are allowed to migrate to the bonding surface, then the bonding process proceeds without interruption, but voids form that disconnect interconnects and render devices inoperable
Solution Approach 1:
The patent converts the harmful migration of contaminants to the bonding surface into a beneficial process by providing designated recessed portions where contaminants are intentionally directed and trapped. Instead of preventing contaminant migration entirely (which would require complex additional processes), the design accepts contaminant migration but redirects it into harmless recessed zones, thereby maintaining bonding process efficiency while ensuring device functionality.
Solution Approach 2:
The recessed portions serve as intermediary trapping zones that intercept contaminants during their natural migration process. This intermediary structure allows the bonding process to proceed uninterrupted (maintaining productivity) while the contaminants are captured in the recesses before they can reach and compromise the bonding interface (preserving reliability).
Data Source
AI summary
A semiconductor device assembly is disclosed. The semiconductor device assembly includes a semiconductor substrate on which a plurality of semiconductor dies are implemented. The semiconductor substrate includes a scribe area between the plurality of semiconductor dies. A layer of passivation material is disposed at a first side of the semiconductor substrate such that the layer of passivation material has one or more recessed portions at the scribe area.