Scribe Seal Insulation for High Voltage Bond Wire Breakdown
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Solution Overview
Problem
High voltage bond wires in Multi-Chip Module (MCM) Small Outline Integrated Circuit (SOIC) packages experience premature breakdown due to strong electric fields caused by their proximity to the surface, leading to potential short circuits and failure, especially when extending over scribe seals and edges, which do not meet stringent voltage requirements.
Innovation Solution
A semiconductor die design featuring a scribe seal with a trench and high breakdown strength dielectric layers covering metal stacks, along with an electrical insulating layer, is implemented to create a barrier between the bond wire and the surface, reducing the risk of electrical breakdown and crack propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bond wires are positioned close to the die surface to reduce package size and improve connectivity, then manufacturing efficiency and electrical connection quality improve, but electric field strength increases causing premature breakdown of isolation material
Solution Approach 1:
The patent introduces an intermediary insulating layer between the bond wire and the die surface. This mediator reduces the electric field strength at the isolation material interface while maintaining the close proximity positioning for manufacturing efficiency. The insulating layer acts as a buffer that prevents direct electrical breakdown without requiring increased wire-to-surface distance.
Solution Approach 2:
The patent modifies the electrical parameters of the interface region by introducing materials with different dielectric properties. By changing the insulating material parameters (dielectric constant, breakdown voltage) in the region between bond wire and die surface, the system achieves both close positioning for productivity and enhanced breakdown resistance through superior material properties.
2Reliability
If scribe seal is exposed at the top surface to prevent crack propagation, then mechanical reliability improves, but electric field concentration increases causing breakdown in high voltage applications
Solution Approach 1:
The patent applies different material qualities to different regions: the scribe seal maintains its exposed metal structure for crack arrest functionality, while the surrounding and adjacent regions receive enhanced insulating coverage. This local differentiation allows the scribe seal to perform its mechanical function while the insulating layer mitigates electric field concentration in critical high voltage areas.
Solution Approach 2:
An insulating layer is introduced as a mediator between the exposed scribe seal metal and the high voltage bond wire region. This intermediary reduces the electric field concentration that would otherwise occur at the exposed metal edges, while the scribe seal itself remains exposed to maintain its crack prevention function.
3Ease of operation
If high voltage bond wires extend over die edges to connect components, then electrical connectivity is achieved, but proximity to grounded scribe seal creates high electric field leading to isolation breakdown
Solution Approach 1:
The patent introduces an insulating layer as a mediator between the high voltage bond wire and the grounded scribe seal. This intermediary maintains the necessary electrical connectivity by allowing the bond wire to extend over die edges while simultaneously preventing breakdown by reducing electric field strength in the isolation region through dielectric properties.
Solution Approach 2:
The patent addresses the two-dimensional proximity problem by introducing a third dimension - a vertical insulating layer covering. Instead of increasing horizontal distance between bond wire and scribe seal (which would affect connectivity), the solution adds vertical insulation coverage that reduces electric field interaction while maintaining horizontal positioning for electrical connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the insulation between bond wires and the die surface, enabling the MCM SOICs to withstand higher voltages and longer operational lifetimes by reducing the risk of electrical breakdown and crack propagation, thus meeting stringent high voltage requirements.
Implementation Method 1
An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer.
Implementation Method 2
A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack.
Data Source
AI summary
A semiconductor die includes a plurality of layers, the plurality of layers having a top surface. A scribe seal is located in the plurality of layers and includes a first metal stack having a first metal layer located proximate the top surface. A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack. An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer.