Scribe Structure for Memory Device Crack Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Low-k insulating materials in semiconductor devices, such as silicon oxycarbide and silicon carbonitride, exhibit weak thermo-mechanical characteristics, leading to adhesion issues and brittleness, which result in cracks during the dicing process and disrupt the formation of conductive seed layers, affecting the yield and functionality of semiconductor devices.
Innovation Solution
A support structure is formed between adjacent semiconductor chips by etching a groove in the scribe region, with a thicker dielectric layer providing support and preventing cracks, and a conductive seed layer is deposited using electroplating to ensure continuous coverage across concave portions of the low-k film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a low-k film is used to reduce parasitic capacitance, then high speed operations are achieved, but adhesion to conductive layers deteriorates and cracks propagate during dicing
Solution Approach 1:
A separate adhesion layer is introduced between the low-k film and the conductive layer to serve as an intermediary that provides strong bonding to both materials, resolving the adhesion problem while maintaining the low-k film's electrical performance benefits
Solution Approach 2:
The structure uses a composite approach by combining the low-k dielectric material with a specially designed adhesion layer that has compatible mechanical and chemical properties with both the low-k film and conductive layer, creating a multi-material system that leverages the strengths of each material
2Reliability
If a groove is formed in the scribe region to reduce cracks, then crack propagation is reduced, but concave portions are created that disrupt conductive seed layer formation
Solution Approach 1:
The groove is formed in advance before the conductive seed layer deposition step, allowing the seed layer to be deposited over the groove structure. The preliminary formation of the groove with proper dimensions ensures that subsequent electroplating can successfully bridge across it, creating a continuous conductive path
Solution Approach 2:
The groove dimensions (depth, width, shape) are carefully controlled and optimized to specific parameter ranges that allow electroplating to successfully bridge across the groove while still providing crack propagation resistance, transforming the groove from a defect into a functional feature
3Speed
If low-k material is used to reduce parasitic capacitance, then high speed operations are achieved, but the material becomes brittle and cracks during dicing
Solution Approach 1:
The adhesion layer serves as a mechanical intermediary that absorbs and distributes stress during dicing, protecting the brittle low-k film from crack propagation while allowing the structure to maintain its electrical performance characteristics
Solution Approach 2:
The adhesion layer is positioned beforehand to provide mechanical cushioning and stress distribution during the dicing process, preventing cracks from initiating or propagating through the low-k film while maintaining the film's integrity for high-speed operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The support structure enhances the mechanical integrity of the semiconductor device during dicing, reducing crack propagation and ensuring a continuous conductive seed layer, thereby improving the yield and functionality of the semiconductor devices.
Implementation Method 1
a conductive seed layer may be formed as an initial step of electroplating of the conductive material
Data Source
AI summary
Apparatuses and methods for manufacturing chips are described. An example method includes: removing a first portion of a cover layer and at least one dielectric layer under the first portion of the cover layer in a cut region between chips to form a groove, and forming a support structure including a second portion of the cover layer and the at least one dielectric layer under the second portion of the cover layer in the cut region; removing a third portion of the cover layer in one of the chips and a portion of the at least one dielectric layer under the third portion of the cover layer to form an hole on the first chip; depositing a conductive layer to cover the cover layer and the hole; forming a conductive pillar on the conductive layer in the hole; and removing the conductive layer on the cover layer and an edge surface of the hole.