Scribing Slot Testing Structure for Polysilicon Gate Strip Width
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Solution Overview
Problem
Conventional photolithography testing methods using scribing slots fail to accurately monitor the strip width of step structures in semiconductor fabrication, leading to abnormal polysilicon gate formation and reduced product yield due to light reflection issues.
Innovation Solution
A testing structure comprising perpendicular isolated lines and field region patterns simulating the LOCOS structure, with strategically placed graphics to accurately represent the step height and distance, allowing for real-time monitoring of strip width and morphology of polysilicon gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a flat source region testing graphic is used in the scribing slot, then the testing process is simple and convenient, but it cannot reflect the actual strip width of step structures in the die, leading to inaccurate measurements
Solution Approach 1:
The testing graphic is designed with different local structures: a flat source region for basic positioning and a step structure region that replicates the actual die topology. Each region serves its specific function - the flat region provides operational simplicity while the step region provides measurement accuracy for polysilicon gate strip widths.
Solution Approach 2:
The testing graphic copies the actual step structure of the polysilicon gate in the die. By replicating the step topology in the scribing slot testing graphic, the measurement conditions closely match the actual production conditions, enabling accurate strip width measurement that reflects real die performance.
2Ease of manufacture
If the testing graphic is formed on a flat silicon substrate, then the photolithography process is straightforward, but light reflection at steps causes photoresist exposure abnormalities and affects strip width
Solution Approach 1:
Instead of avoiding the step structure that causes light reflection, the invention incorporates the step structure into the testing graphic design. The harmful reflection effect is converted into a beneficial test condition that reveals actual exposure abnormalities, allowing the photolithography process to be optimized for the specific step topology.
Solution Approach 2:
The testing graphic with step structure is formed in advance in the scribing slot before actual die production. This preliminary testing structure allows identification of photoresist exposure abnormalities and photolithography parameter issues before they affect actual die manufacturing, enabling preventive process optimization.
3Productivity
If a unified testing graphic rule is applied to all products, then real-time monitoring is efficient and convenient, but it fails to detect abnormalities specific to step structures like polysilicon gates
Solution Approach 1:
The testing graphic is segmented into multiple functional regions: a flat source region for general positioning and alignment, and a step structure region specifically for testing polysilicon gate strip widths. This segmentation allows the single testing graphic to perform both general monitoring and specific step-structure detection functions simultaneously.
Solution Approach 2:
The testing graphic in the scribing slot serves multiple functions: it provides general strip width monitoring for all products through the flat region, and specifically detects polysilicon gate abnormalities through the step structure region. This multi-functionality maintains real-time monitoring efficiency while adding specialized detection capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate online testing and correction of strip width and morphology issues, improving polysilicon gate formation and enhancing product yield by simulating the actual step structure conditions.
Implementation Method 1
transferring the testing structure for the strip width of the scribing slot to a scribing slot on a wafer by performing a photolithography process
Implementation Method 2
because of the step, vertical incident light will reflect on the other direction
Data Source
AI summary
A testing structure of a strip width of a scribing slot is provided, the structure includes a first isolated line (232) and a second isolated line (234) which are perpendicular to each other, the testing structure further includes a first field region pattern (220), the first field region pattern (220) includes two graphics, the two graphics are each located on one side of the first isolated line (232) and opposite to each other. A testing method of a strip width of a scribing slot is also disclosed. Graphics of the field oxide region simulating the LOCOS structure are provided on two sides of the isolated line, the step is artificially generated, a polysilicon gate graphic on a small size source region formed by photolithography can be displayed through online testing of the strip width or online displaying and checking of the strip width, thus a practical situation of the die can be known, an abnormity of the strip width and morphology of the polysilicon gate caused by a reflection of a substrate can be found instantly.