SCRMOS Transistor Drain Segmentation for ESD Reliability
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Solution Overview
Problem
MOS transistors integrated with silicon controlled rectifier (SCR) devices, known as SCRMOS transistors, experience reliability degradation due to high voltage transients such as electrostatic discharge (ESD) events, which cause localized charge carrier injection and potential device damage.
Innovation Solution
The design incorporates SCRMOS transistors with multiple drain structures, where at least one drain structure features a centralized drain diffused region and a distributed SCR terminal, with an MOS gate electrically coupled to an adjacent source diffused region to prevent inversion layer formation and control breakdown, thereby reducing current filament formation during ESD events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SCRMOS transistor uses lightly doped drain region for normal operation, then device performance is maintained, but reliability degrades during high voltage transients due to localized charge carrier injection
Solution Approach 1:
The drain structure is segmented into multiple independently doped regions (first drain region with first doping concentration and second drain region with second doping concentration). This segmentation allows different portions of the drain to have different doping levels, enabling the lightly doped region to maintain normal device performance while the heavily doped region prevents localized charge carrier injection during high voltage transients, thus resolving the contradiction between reliability and harmful factors.
Solution Approach 2:
Different regions of the drain structure are assigned different doping concentrations to perform different functions. The first drain region has a first doping concentration optimized for normal operation, while the second drain region has a second doping concentration specifically designed to prevent charge carrier injection during ESD events. This local differentiation of quality (doping concentration) allows the device to simultaneously achieve good normal operation and high reliability during transients.
2Reliability
If drain region is heavily doped to prevent charge carrier injection, then reliability during transients improves, but device performance during normal operation degrades
Solution Approach 1:
The drain is divided into separate regions with different doping concentrations. The first drain region maintains lower doping for optimal normal operation performance, while the second drain region uses higher doping to prevent charge carrier injection during transients. This segmentation allows each region to be optimized for its specific function without compromising the other.
Solution Approach 2:
The doping concentration is locally optimized in different drain regions. The first drain region has doping concentration tailored for normal operation, while the second drain region has higher doping concentration specifically for transient protection. This local quality differentiation enables the device to achieve both good productivity during normal operation and high reliability during transients.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability of SCRMOS transistors by reducing current filament formation and device damage during high voltage transients, improving the overall performance and durability of integrated circuits.
Implementation Method 1
An MOS gate adjacent to each drain structure having a centralized drain diffused region is electrically coupled to a corresponding adjacent source diffused region
Data Source
AI summary
An integrated circuit containing an SCRMOS transistor. The SCRMOS transistor has one drain structure with a centralized drain diffused region and distributed SCR terminals, and a second drain structure with distributed drain diffused regions and SCR terminals. An MOS gate between the centralized drain diffused region and a source diffused region is shorted to the source diffused region. A process of forming the integrated circuit having the SCRMOS transistor is also disclosed.