ScS Josephson Junction Qubits With Single-Step Lithography
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Solution Overview
Problem
Conventional superconducting qubit devices face challenges in scaling due to complex fabrication processes involving multiple lithography steps and sensitivity to charge noise, particularly with aluminum-based Josephson junctions.
Innovation Solution
The development of co-planar superconductor-constriction-superconductor Josephson junctions (ScS JJs) fabricated using a single lithography step, allowing for simultaneous patterning of Josephson junctions, capacitors, and resonators from the same thin film superconductor, reducing complexity and enhancing resistance to charge noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional SIS Josephson junctions are fabricated using multiple lithography steps with double-angle metallization, then manufacturing precision is improved, but device complexity and fabrication time increase
Solution Approach 1:
The patent combines multiple lithography steps into a single lithography step by using a self-aligned fabrication process. The SIS Josephson junction, capacitor, and resonator are all patterned simultaneously in one lithography step, eliminating the need for separate lithography steps and double-angle metallization processes. This merging of steps reduces fabrication complexity while maintaining manufacturing precision through self-alignment.
Solution Approach 2:
The patent segments the fabrication process into distinct functional regions that can be patterned in a single step. By designing the Josephson junction, capacitor, and resonator as integrated structures that share common alignment references, the complex multi-step process is replaced with a unified single-step patterning approach that achieves the same functional segmentation without the complexity of multiple lithography steps.
2Ease of manufacture
If aluminum-based SIS Josephson junctions are used, then manufacturing ease is improved, but sensitivity to charge noise increases
Solution Approach 1:
The patent applies local quality by using aluminum-based SIS Josephson junctions specifically in regions where ease of manufacture is critical, while incorporating design features such as shunting capacitors and geometric configurations that locally reduce charge noise sensitivity. The self-aligned fabrication process ensures precise positioning of these noise-mitigation features relative to the Josephson junction, providing localized protection against charge noise while maintaining the manufacturing advantages of aluminum-based materials.
3Manufacturing precision
If separate lithography steps are used for Josephson junctions and other device components, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent merges the patterning of Josephson junctions, capacitors, and resonators into a single lithography step using a self-aligned process. This consolidation maintains manufacturing precision by ensuring automatic alignment between different components through shared alignment references, while simultaneously improving productivity by eliminating the time required for multiple sequential lithography steps and the intermediate processing steps between them.
4Reliability
If ion milling is used to remove native oxide layers, then reliability is improved, but device complexity and processing time increase
Solution Approach 1:
The patent applies preliminary action by performing oxide removal immediately before Josephson junction formation within the same fabrication sequence, and using in-situ processes that eliminate the need for separate ion milling steps. The self-aligned fabrication process ensures that surfaces are prepared and protected from re-oxidation between steps, maintaining reliable superconductor contacts without adding complex intermediate processing steps or extending fabrication time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process and provides improved resistance to charge noise, enabling more robust and scalable superconducting qubit devices with lower anharmonicity and longer coherence times.
Implementation Method 1
The core of a known superconducting qubit is one or more superconductor/insulator/superconductor Josephson junctions (SIS JJs), which are typically formed from a thin film sandwich structure of aluminum, aluminum oxide, aluminum (Al/AlOx/Al)
Implementation Method 2
the shunting capacitors and the microwave resonators are often made from other superconductors, such as for example, niobium (TC=9.2 K), tantalum (TC=4.4 K), and titanium nitride (TC=5.6 K)
Data Source
AI summary
One or more embodiments relate to a superconducting qubit architecture that can be fabricated in one standard patterning step such as a lithographical step for example. Specifically, embodiments relates to a superconductor-constriction-superconductor Josephson junction (ScS JJ) qubit device for use in a quantum information processing environment. In one or more embodiments, the qubit device includes a substrate (a semiconductor substrate, an insulator substrate, and a dielectric substrate for example); a first superconducting pad formed on the substrate; and a second superconducting pad formed on the substrate, where the second superconducting pad coupled to and coplanar with the first superconducting pad.