SCVR Packaging with Discrete IPDs for Low-Parasitic Power Delivery
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Solution Overview
Problem
Existing power management systems with on-chip switched capacitor voltage regulators face limitations in achieving high efficiency due to constraints on capacitor density, parasitics, and processing node compatibility, which affect their ability to support multiple circuit loads and varying power conditions.
Innovation Solution
The implementation of discrete integrated passive devices (IPDs) packaged separately from the SCVR circuitry, allowing for advanced processing nodes, high capacitor density, and efficient packaging techniques such as integrated fan-out, 2.5D, and chip-on-wafer configurations, which enhance SCVR efficiency by reducing parasitics and increasing pin density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If capacitors are integrated on-chip with SCVR circuitry, then device complexity is reduced, but capacitor density is limited and parasitics increase
Solution Approach 1:
The patent segments the SCVR system into separate functional components: the SCVR circuitry remains on-chip while capacitors are implemented as discrete integrated passive devices (IPDs) packaged separately. This segmentation allows each component to be optimized independently - the circuitry for low complexity and the capacitors for high density with reduced parasitics.
Solution Approach 2:
The patent extracts the capacitor elements from the on-chip integration and packages them as separate IPDs. This extraction removes the parasitic limitations and density constraints of on-chip capacitors while maintaining electrical connection through the packaging interface, thereby improving overall SCVR efficiency.
2Ease of manufacture
If on-chip capacitors are used, then manufacturing is simpler, but parasitics increase and efficiency decreases
Solution Approach 1:
By segmenting the capacitor function into separate IPDs, the patent enables specialized fabrication processes optimized for low-parasitic capacitor structures while keeping the SCVR circuitry manufacturing unchanged. This segmentation resolves the conflict between manufacturing simplicity and efficiency.
Solution Approach 2:
The patent introduces an intermediary packaging structure that connects the on-chip SCVR circuitry to the separately packaged IPD capacitors. This intermediary interface allows the system to benefit from both on-chip integration and discrete capacitor advantages, achieving low parasitics without sacrificing manufacturing feasibility.
3Loss of energy
If discrete IPDs are used, then capacitor density increases and parasitics reduce, but device complexity increases
Solution Approach 1:
The patent employs nested packaging structures where IPDs are integrated within the system package or co-packaged with the SCVR circuitry. This nesting approach minimizes the physical footprint and interconnection complexity while maintaining the benefits of discrete capacitors, thereby reducing the perceived device complexity.
Solution Approach 2:
The patent utilizes three-dimensional packaging arrangements and vertical interconnections to accommodate discrete IPDs without significantly increasing the planar footprint. By transitioning to vertical stacking and multi-layer interconnects, the system achieves high capacitor density with manageable complexity.
4Device complexity
If on-chip capacitors are used, then pin density requirements are lower, but supporting multiple circuit loads becomes difficult
Solution Approach 1:
By segmenting the capacitor resources into separate IPDs, the patent enables independent optimization and allocation of capacitor resources to multiple circuit loads. Each IPD can be dedicated to specific load requirements, improving adaptability without increasing pin density on the main chip.
Solution Approach 2:
The separately packaged IPDs serve multiple functions: they provide capacitance for the SCVR operation, enable support for multiple circuit loads with different power requirements, and can be configured in different packaging arrangements. This multi-functionality resolves the contradiction between pin density and load support capability.
Data Source
AI summary
Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.