Self-Aligned S/D Capping Layer for Via Isolation Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing is to form vias on source/drain contacts without breaking through the liner layer, which often leads to a reduced distance between metal gates and source/drain contact vias, increasing the risk of short circuits due to metal leakage and complicating the manufacturing process.
Innovation Solution
A process is developed that involves depositing an inhibitor layer selectively on the source/drain contacts, preventing the deposition of a dielectric material, and forming a liner layer on the sidewalls of self-aligned capping trenches, avoiding vertical etching and maintaining the integrity of the liner layer, thereby enhancing process robustness and Time Dependent Dielectric Breakdown performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the liner layer is broken through to form vias on source/drain contacts, then via formation is achieved, but the distance between metal gates and source/drain contact vias is reduced, increasing short circuit risk
Solution Approach 1:
A self-aligned capping layer is formed over the source/drain contacts before via hole etching. This capping layer extends laterally beyond the gate spacer edges, creating a protective structure in advance that prevents liner layer breakthrough and maintains adequate spacing between metal gates and source/drain contact vias during subsequent processing.
Solution Approach 2:
The self-aligned capping layer acts as an intermediary structure between the gate spacers and source/drain contacts. It provides a protective barrier that prevents direct exposure and potential short circuits, while maintaining the necessary electrical isolation and mechanical support during via formation processes.
2Ease of manufacture
If the liner layer is broken through during via hole etching, then via formation is enabled, but manufacturing process complexity increases
Solution Approach 1:
The self-aligned capping layer is formed in advance with lateral extension beyond gate spacer edges, establishing a predetermined protective structure that simplifies subsequent via hole etching by eliminating the need for precise liner layer breakthrough control and reducing process variability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enlarges the contact area between the via and the source/drain contact while maintaining good isolation, improving process robustness and reducing the risk of short circuits, thereby enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
selectively depositing an inhibitor layer on the source/drain contact but not on surfaces of the first capping layer and not on top surfaces of the gate spacers
Data Source
AI summary
A semiconductor structure includes a substrate; a first structure over the substrate and having a first gate stack and two first gate spacers on two opposing sidewalls of the first gate stack; a second structure over the substrate and having a second gate stack and two second gate spacers on two opposing sidewalls of the second gate stack; a source/drain (S/D) feature over the substrate and adjacent to the first and the second gate stacks; an S/D contact over the S/D feature and between one of the first gate spacers and one of the second gate spacers; a conductive via disposed over and electrically connected to the S/D contact; and a dielectric liner layer. A first portion of the dielectric liner layer is disposed on a sidewall of the one of the first gate spacers and is directly above the S/D contact and spaced from the S/D contact.