S/D Dielectric Seed Layer for Strained Epitaxial Channel Performance
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Solution Overview
Problem
The scaling down of semiconductor devices leads to increased complexity and difficulty in process control, with amorphous portions in source/drain (S/D) dielectric structures causing higher resistance and lower carrier mobility, resulting in reduced direct current (DC) device performance due to strain loss on nanostructure transistors.
Innovation Solution
A semiconductor seed layer is formed on the S/D dielectric structures, with an epitaxial structure comprising a non-crystalline and crystalline portion, reducing resistance and increasing carrier mobility by straining the channel structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If amorphous portions are present in source/drain dielectric structures, then device dimensions can be scaled down, but resistance increases and carrier mobility decreases
Solution Approach 1:
The patent extracts and removes the amorphous portions from the source/drain dielectric structures through selective etching processes. This extraction eliminates the harmful amorphous regions while preserving the crystalline portions, thereby reducing resistance and improving carrier mobility without sacrificing device scaling benefits
Solution Approach 2:
The patent applies local quality by creating distinct regions within the source/drain structure: crystalline portions with high carrier mobility and low resistance, and removed amorphous portions. This local differentiation ensures that only the beneficial crystalline regions remain, optimizing electrical performance in critical areas while maintaining overall device scaling
2Ease of manufacture
If amorphous portions are present in source/drain dielectric structures, then manufacturing can be simplified, but DC device performance decreases due to strain loss
Solution Approach 1:
The patent performs preliminary action by forming the amorphous portions during the initial source/drain dielectric structure fabrication, then subsequently removing them through selective etching. This preliminary formation followed by removal allows for simplified manufacturing processes while ensuring that the harmful amorphous regions are eliminated before final device assembly, thereby preserving strain and DC performance
Solution Approach 2:
The patent converts the potentially harmful amorphous portions into a beneficial process intermediate. By intentionally forming amorphous regions during fabrication and then selectively removing them, the process simplifies manufacturing while ensuring high-quality crystalline source/drain structures that maintain strain and DC device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances DC device performance by reducing resistance and increasing carrier mobility through the strain imparted by the epitaxial structure on the channel, improving overall device performance.
Implementation Method 1
increasing carrier mobility by straining the channel structure
Data Source
AI summary
The present disclosure describes a semiconductor device having a semiconductor seed layer on a S/D dielectric structure. The semiconductor structure includes a channel structure on a substrate, a gate structure wrapped around the channel structure, an inner spacer adjacent to end portions of the gate structure and the channel structure, a dielectric structure on the substrate and adjacent to the inner spacer, a non-crystalline semiconductor material on the dielectric structure, and an epitaxial structure on top surfaces of the non-crystalline semiconductor material and the dielectric structure.