S/D Epitaxial Shape Control Near Isolation Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In CMOS FETs, the downscaling of integrated circuits and increasing speed demands require more effective measures to prevent drain-induced barrier lowering (DIBL) and latch-up, particularly due to insufficient growth of source/drain epitaxial layers near insulating layers, leading to reduced driving current and asymmetric device characteristics.
Innovation Solution
A method and structure are provided to improve the growth of source/drain epitaxial layers by forming a cover layer that exposes the active region between isolation and gate structures, allowing for recess formation and epitaxial layer growth, ensuring sufficient stress and symmetry, which involves forming a cover layer over the gate structures and etching the active region to create recesses for epitaxial growth, using SiGe or SiP layers for compressive or tensile stress, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If source/drain epitaxial layers are grown in conventional recesses, then device fabrication can proceed, but the epitaxial layers grow insufficiently near insulating layers leading to reduced driving current and asymmetric device characteristics
Solution Approach 1:
A cover layer is formed over the gate structures and isolation structure before recess formation. This preliminary action protects the isolation structure and defines a controlled growth region, ensuring that the epitaxial layer grows symmetrically from the active region without being constrained by the isolation structure, thereby achieving sufficient growth and symmetric characteristics.
Solution Approach 2:
The cover layer acts as an intermediary element between the gate structures/isolation structure and the epitaxial layer. It provides a controlled interface that enables uniform epitaxial growth by preventing direct interaction between the epitaxial layer and the isolation structure, thus achieving symmetric device characteristics and sufficient driving current.
2Productivity
If source/drain epitaxial layers are grown near isolation structures, then device integration is achieved, but asymmetric device characteristics occur due to insufficient growth
Solution Approach 1:
The cover layer is formed in advance to define the growth boundary before epitaxial layer formation. This preliminary structure ensures that the epitaxial layer grows uniformly from the active region without asymmetric constraints from the isolation structure, achieving both sufficient growth for high driving current and symmetric device characteristics.
Solution Approach 2:
The cover layer creates a localized controlled environment for epitaxial growth specifically at the interface between the gate structures and the active region. This local modification ensures uniform growth conditions in the critical area, achieving symmetric device characteristics while maintaining high driving current through sufficient epitaxial layer development.
3Ease of manufacture
If conventional recess formation is used, then fabrication process is simple, but latch-up occurs due to insufficient epitaxial layer growth
Solution Approach 1:
The cover layer is formed as a preliminary structure before recess formation and epitaxial layer growth. This additional step, while increasing fabrication complexity slightly, ensures sufficient epitaxial layer growth that prevents latch-up, thereby improving device reliability without significantly complicating the overall manufacturing process.
Solution Approach 2:
The cover layer serves as an intermediary that enables controlled epitaxial growth in the recess region. By providing this intermediate structure, the epitaxial layer can grow sufficiently to prevent latch-up while maintaining a relatively simple fabrication process that builds upon conventional techniques.
4Reliability
If epitaxial layer growth is constrained by isolation structure, then device integration is achieved, but carrier mobility is reduced
Solution Approach 1:
The cover layer acts as an intermediary between the isolation structure and the epitaxial layer, providing a controlled growth interface that enables sufficient epitaxial layer development. This intermediary structure allows the epitaxial layer to grow with adequate thickness and quality, improving carrier mobility while maintaining proper device integration through the cover layer's protective and defining functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility, increases driving current, reduces leakage current, and improves DIBL properties by ensuring a larger and symmetric epitaxial layer growth, thus addressing the issues of latch-up and asymmetric device characteristics.
Implementation Method 1
an epitaxial semiconductor layer is formed in the recess... ensuring sufficient stress and symmetry... using SiGe or SiP layers for compressive or tensile stress, respectively
Data Source
AI summary
In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.