Nanosheet Source/Drain Isolation Structure for Leakage and Capacitance
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Solution Overview
Problem
Nanosheet transistors face challenges such as current leakage between source/drain and substrate due to direct contact, and high parasitic capacitance between source/drain and metal gate, leading to reduced gate control and performance issues.
Innovation Solution
An isolation layer is formed on the bottom surface of the source/drain trench to prevent substrate contact, and air gaps are created between the source/drain feature and the substrate and inner spacers, allowing the source/drain feature to be epitaxially grown only from channel semiconductor layers, thereby reducing leakage and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source/drain features are epitaxially grown from substrate and channel semiconductor layers, then device structure is formed, but current leakage occurs between source/drain and substrate
Solution Approach 1:
The source/drain structure is segmented into multiple regions: the first source/drain region grown from substrate, the second source/drain region grown from channel layers, and an air gap separating them. This segmentation prevents direct current leakage path while maintaining epitaxial growth benefits.
Solution Approach 2:
An air gap is introduced as an intermediary between the substrate-grown source/drain region and the channel layer-grown source/drain region. This air gap acts as a barrier to current leakage while allowing the epitaxial growth process to continue.
2Ease of manufacture
If source/drain features physically connect inner spacers surrounding metal gate, then device structure is formed, but high parasitic capacitance occurs between source/drain and metal gate
Solution Approach 1:
The physical connection between source/drain features and inner spacers is removed by creating an air gap. This extraction of the harmful direct contact eliminates the high parasitic capacitance while preserving the overall device structure formation.
3Device complexity
If bottom single gate device is formed with substrate, S/D features and metal gate, then device structure is created, but high leakage occurs due to less gate control
Solution Approach 1:
The gate control structure is segmented into a top metal gate providing double gate control and a bottom gate electrode separated by air gap preventing unwanted bottom single gate formation. This segmentation enables effective gate control while avoiding leakage issues.
Solution Approach 2:
An air gap is introduced as an intermediary between the substrate and the bottom gate electrode, preventing the formation of a leaky bottom single gate device while allowing the top metal gate to provide effective double gate control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates bulk leakage current and parasitic capacitance, enhancing the performance of nanosheet transistors by ensuring the source/drain feature is isolated from the substrate and reducing unwanted capacitance.
Implementation Method 1
an isolation layer is formed on the bottom surface of the source/drain trench to prevent substrate contact
Implementation Method 2
air gaps are created between the source/drain feature and the substrate and inner spacers, allowing the source/drain feature to be epitaxially grown only from channel semiconductor layers, thereby reducing leakage and capacitance
Implementation Method 3
the source/drain feature is epitaxially grown only from channel semiconductor layers
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.