SD/MMC Bridge Circuit for Direction Detection Without Control Signals
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Solution Overview
Problem
Conventional bi-directional SD and MMC bus systems require external directional signals and decoding of bus transactions to determine signal direction, leading to increased overhead and cost, especially in advanced silicon processes that do not support higher voltages, and pose challenges in bridging SD devices without directional signals.
Innovation Solution
The implementation of two data buffers that drive signals in opposite directions, with special logic to enable and disable them based on sampled bits at terminals, allowing for determination of signal direction without external directional signals or exact bus transaction decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external directional signals and bus transaction decoding are used to determine signal direction, then signal direction can be accurately determined, but overhead and cost increase
Solution Approach 1:
The system determines signal direction autonomously by monitoring voltage levels on the bi-directional bus without requiring external directional signals. The level shifter circuitry automatically detects whether terminal A or terminal B is driving the bus by sampling voltage levels, eliminating the need for separate direction control pins and reducing system complexity while maintaining accurate direction determination
Solution Approach 2:
The patent replaces the mechanical/electrical approach of using external directional signals and complex decoding logic with an electrical voltage-level monitoring approach. By sampling voltage levels at the terminal and comparing them against expected levels for each direction, the system determines signal direction through electrical measurement rather than complex signal processing
2Adaptability or versatility
If level shifters are used to support voltage translation between 1.8V and 3.6V, then voltage compatibility is achieved, but direction determination becomes more complex
Solution Approach 1:
The level shifter circuit performs multiple functions: it translates voltages between 1.8V and 3.6V levels while simultaneously determining signal direction through voltage level sampling. This multi-functionality eliminates the need for separate direction detection circuitry, reducing overall system complexity while maintaining voltage compatibility across different process nodes
Solution Approach 2:
The level shifter acts as an intermediary between terminals with different voltage domains (1.8V and 3.6V), and in the process of mediating voltage translation, it inherently provides direction information through its voltage sampling mechanism. This intermediary function resolves both the voltage compatibility issue and the direction determination issue in a unified approach
3Adaptability or versatility
If bi-directional data buses are implemented, then signal transmission flexibility is improved, but direction determination overhead increases
Solution Approach 1:
The bi-directional bus system automatically determines transmission direction through voltage level monitoring without requiring external direction control signals. The terminal samples voltage levels on the bus and autonomously determines whether it is receiving or transmitting, eliminating the overhead associated with external directional signaling while maintaining full bi-directional flexibility
Data Source
AI summary
A method for determining direction of signal transmission in a bi-directional signal line, including sampling data signals at two terminals, A and B, enabling data flow from A to B when data flow from B to A is not enabled, and a logical 0 bit is sampled at A, enabling data flow from B to A when data flow from A to B is not enabled, and a logical 0 bit is sampled at B, disabling data flow from A to B when data flow from A to B is enabled and two successive logical 1 bits are sampled at A, and disabling data flow from B to A when data flow from B to A is enabled and two successive logical 1 bits are sampled at B. An electrical circuit is also described and claimed.