SD/MMC Bus Bridge Circuit With Self-Directed Signal Switching
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Solution Overview
Problem
Conventional bi-directional SD and MMC bus systems require external directional signals and decoding of bus transactions to determine signal direction, leading to increased overhead and cost, particularly in devices that need to bridge SD signals without directional information.
Innovation Solution
The implementation of a circuit with two data buffers and logical gates that enable and disable signal transmission based on sampled bits at terminals A and B, allowing for bi-directional signal transmission without external directional signals or exact content decoding, using tri-state buffers and data flip-flop modules to manage signal direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level shifters are used for bi-directional SD and MMC buses, then voltage level translation is achieved, but external directional signals and content decoding are required increasing overhead and cost
Solution Approach 1:
The level shifter autonomously determines signal direction by monitoring voltage levels on the bi-directional bus lines itself, without requiring external directional control signals. The circuit self-activates when it detects a voltage drop indicating a '0' bit transmission, eliminating the need for separate direction control pins and reducing system complexity
Solution Approach 2:
The level shifter continuously monitors the voltage levels on the SD/MMC bus lines and uses this feedback to automatically control its enable/disable state. When a '0' bit is detected (voltage drops to Vss), the level shifter enables itself to translate the voltage level, and disables when '1' bits are present (voltage at Vdd), creating a closed-loop automatic direction detection system
2Adaptability or versatility
If bi-directional data buses are implemented, then data transmission flexibility is improved, but signal direction determination requires additional directional signals increasing device complexity
Solution Approach 1:
The level shifter autonomously determines signal direction by monitoring voltage levels on the bi-directional bus lines itself, without requiring external directional control signals. The circuit self-activates when it detects a voltage drop indicating a '0' bit transmission, eliminating the need for separate direction control pins and reducing system complexity
Solution Approach 2:
The same level shifter circuit handles both voltage translation and direction detection functions that were previously separated into distinct components. The circuit works with standard SD and MMC protocols without requiring modified directional control signals, making it universally applicable to existing bi-directional bus implementations
3Reliability
If level shifters require external directional signals, then proper voltage translation is achieved, but integrated circuits must support additional directional signals increasing overhead and cost
Solution Approach 1:
The level shifter autonomously determines signal direction by monitoring voltage levels on the bi-directional bus lines itself, without requiring external directional control signals. The circuit self-activates when it detects a voltage drop indicating a '0' bit transmission, eliminating the need for separate direction control pins and reducing system complexity
Solution Approach 2:
The directional signal requirement is extracted and eliminated from the system. Instead of needing separate directional control signals, the level shifter derives direction information directly from the data signals themselves by monitoring voltage levels, removing the overhead of additional control lines
Data Source
AI summary
A circuit with bi-directional signal transmission, including a first signal source, for generating a first signal comprising one bit per clock cycle during a first plurality of clock cycles, a second signal source, for generating a second signal including one bit per clock cycle during a second plurality of clock cycles, a first buffer, coupled with the first signal source, that outputs the first signal when the first buffer is enabled, a second buffer, coupled with the second signal source, that outputs the second signal when the second buffer is enabled, and a plurality of logical gates, coupled with the first signal source, the second signal source, the first buffer and the second buffer, that control enablement of the first buffer and the second buffer, such that (i) at any given clock cycle at least one of the first buffer and the second buffer is disabled, and (ii) when the first buffer and said the buffer are both disabled, subsequent generation of a ‘0’ bit in the first signal or the second signal causes enablement of the first buffer or the second buffer, respectively.