S/D Template Layer Reduces Strain Loss in Nanosheet Channels
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Solution Overview
Problem
Current nanosheet-based transistor fabrication methods face challenges in minimizing strain loss in spaced-apart or suspended nanosheet channels, which affects carrier mobility and switching speed.
Innovation Solution
The implementation of a source or drain (S/D) template layer made of a continuous semiconductor material within the S/D trench, which is lattice-matched with the S/D region to enable low-defect epitaxial growth, thereby minimizing strain loss and imparting strain to the non-sacrificial nanosheets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spaced-apart nanosheet channels are used to improve gate control, then electrostatic control is improved, but strain loss occurs during fabrication
Solution Approach 1:
A template layer is introduced as an intermediary structure between the sacrificial nanosheets and the final S/D regions. This template layer maintains the spaced-apart configuration for electrostatic control while providing a continuous material structure that prevents strain loss during fabrication. The template layer acts as a mediator that reconciles the conflicting requirements of spatial separation and strain preservation.
Solution Approach 2:
The template layer is formed before the S/D regions are created, establishing a pre-configured structure that will maintain strain throughout subsequent fabrication steps. By performing the template formation action in advance, the strain-preserving framework is established before any strain-loss mechanisms can occur during later processing.
2Loss of energy
If continuous S/D template layer is formed to reduce strain loss, then strain preservation is improved, but manufacturing complexity increases
Solution Approach 1:
The template layer serves multiple functions simultaneously: it maintains the spaced-apart nanosheet configuration for electrostatic control, prevents strain loss during fabrication, and provides a structural framework for subsequent S/D region formation. By consolidating these multiple functions into a single structure, the overall manufacturing complexity is managed despite the added functionality.
3Speed
If doped S/D region is formed on template layer, then carrier mobility is improved, but process steps increase
Solution Approach 1:
The doping process is merged with the S/D region formation process that occurs on the template layer. Rather than treating doping as a separate, independent step, it is combined with the epitaxial growth or material deposition process that creates the S/D regions, thereby achieving carrier mobility enhancement without proportionally increasing the total process step count.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces strain loss and enhances carrier mobility, leading to improved transistor performance characteristics such as increased switching speed and reduced energy consumption.
Implementation Method 1
A S/D template layer includes a continuous layer of a first type of semiconductor material, wherein the S/D template layer is within a portion of the S/D trench, on the bottom surface of the S/D trench, and on the sidewalls of the S/D trench. A doped S/D region is on the S/D template layer and within the S/D trench. In some aspects of the invention, the doped S/D region includes a second type of semiconductor material configured to induce strain in the spaced-apart non-sacrificial nanosheets.
Data Source
AI summary
Embodiments of the invention are directed to a semiconductor-based structure that includes a stack having spaced-apart non-sacrificial nanosheets. A source or drain (S/D) trench is adjacent to the stack, wherein the S/D trench includes a bottom surface and sidewalls. A S/D template layer includes a continuous layer of a first type of semiconductor material, wherein the S/D template layer is within a portion of the S/D trench, on the bottom surface of the S/D trench, and on the sidewalls of the S/D trench. A doped S/D region is on the S/D template layer and within the S/D trench. In some aspects of the invention, the doped S/D region includes a second type of semiconductor material configured to induce strain in the spaced-apart non-sacrificial nanosheets.