SDA Bus Error Detection for CE1 Read-Write Conflicts
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Solution Overview
Problem
Existing serial communication protocols like I3C face challenges with error type CE1, where a controller's intended write transaction is misinterpreted by a target as a read transaction, leading to conflicting data on the serial data bus, which current circuitry fails to address effectively.
Innovation Solution
A controller with external logic circuitry monitors and compares data on the SDA line with output data to detect CE1 errors, disabling the output SDA pad buffer and causing a stop condition to resolve the conflict.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If commercially available circuitry (IP block) is used to enable controller to support serial communication, then device complexity is reduced and ease of manufacture is improved, but the circuitry cannot properly support CE1 error condition detection and handling
Solution Approach 1:
The patent divides the error detection and handling function into a separate external logic circuit module that is independent from the commercially available IP block. This segmentation allows the IP block to remain simple and manufacturable while adding specialized error detection capability through the external logic circuit that monitors SDA line data and compares it with output data to detect CE1 errors.
Solution Approach 2:
The patent introduces an external logic circuit as an intermediary between the IP block and the SDA line. This intermediary monitors the communication between the IP block and the bus, detects CE1 errors by comparing monitored data with output data, and triggers appropriate error handling sequences including disabling the output buffer and asserting stop conditions.
2Device complexity
If the controller uses standard circuitry without external logic, then device complexity is low, but CE1 errors cause prolonged data conflicts leading to increased power consumption and potential damage
Solution Approach 1:
The patent implements preliminary error detection by continuously monitoring the SDA line data during normal communication operations. The external logic circuit compares the monitored data with the controller's output data in real-time, enabling early detection of CE1 errors before they can cause prolonged conflicts, excessive power consumption, or potential damage to the communication bus.
Solution Approach 2:
The patent establishes a feedback mechanism where the external logic circuit continuously monitors the SDA line, compares monitored data with intended output data, and provides feedback when discrepancies are detected. Upon detecting a CE1 error, the feedback triggers immediate corrective actions including disabling the output buffer and asserting stop conditions, thereby preventing harmful effects.
3Reliability
If external logic circuitry is added to detect CE1 errors, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the error detection function into a separate external logic circuit, keeping the core IP block simple while adding specialized functionality externally. This modular approach improves error detection capability without significantly complicating the main controller design.
Solution Approach 2:
The external logic circuit is designed to autonomously monitor the SDA line, compare data, detect CE1 errors, and trigger appropriate error handling sequences without requiring complex integration with the IP block. This self-service capability minimizes the complexity overhead while maintaining high error detection capability.
Data Source
AI summary
A controller is provided that includes a serial data (SDA) line interface to connect the controller to an SDA line of a two-wire, shared, serial data bus. The controller includes a circuitry to provide output data for transfer on to the SDA line via the output SDA pad buffer. The controller includes a logic circuit that is external to the circuitry, and that monitors data on the SDA line while the output data is transferred on to the SDA line. The logic circuit compares the monitored data on the SDA line and the output data to detect an error condition when the monitored data and the output data differ. The logic circuit disables an output SDA pad buffer of the SDA line interface for a current byte of the output data provided by the circuitry, and then causes a stop condition on the data bus.