Self-Aligned Post-Cut SDB FinFET Device With Air-Filled Trenches

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Solution Overview

Problem

The existing methods for manufacturing FinFET devices face challenges in controlling fin loss during the FCVD annealing process, which affects the polysilicon gate coverage and subsequent SiGe and SiP epitaxial growth, leading to suboptimal device performance.

Innovation Solution

A self-aligned post-cut SDB FinFET device manufacturing method is developed, involving the formation of fin structures with a SiN layer and hard mask layers, followed by oxide dielectric layer deposition and annealing, etching, and polysilicon layer processing to create SDB trenches filled with air, which reduces fin loss and maintains high-quality SiGe and SiP region growth without additional costs or complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If FCVD annealing process is used to form oxide dielectric layer, then the oxide layer can be deposited covering substrate and fin sidewalls, but fin loss occurs causing channel CD expansion and poor polysilicon gate coverage

Engineering Contradiction:

Improvefin loss controlVSAvoidpolysilicon gate coverage

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

A thin oxide layer is deposited on fin sidewalls before the FCVD annealing process to serve as a protective barrier. This preliminary protective layer prevents excessive fin loss during the subsequent annealing step, ensuring that the fin structures maintain their dimensions and the polysilicon gate can properly cover the SDB region.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The thin oxide layer acts as a cushioning protective layer that absorbs or mitigates the harmful effects of the FCVD annealing process on the fin structures. By placing this protective layer beforehand, the patent prevents the fin loss that would otherwise occur during thermal processing.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Manufacturing precision

If self-aligned process is used for SDB trench formation, then manufacturing complexity is reduced and alignment precision is improved, but additional process steps are required

Engineering Contradiction:

Improvealignment precisionVSAvoidprocess steps

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines multiple functions into the polysilicon deposition step: the polysilicon layer serves as both the gate material and the etch stop layer for defining SDB trench positions. This merging of functions enables self-alignment without requiring separate alignment steps, reducing overall manufacturing complexity while maintaining high alignment precision.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The polysilicon layer performs multiple roles: it forms the gate structure, provides an etch stop for SDB trench definition, and enables self-aligned patterning. This multi-functionality reduces the need for additional dedicated alignment layers or steps, simplifying the overall process despite the self-aligned requirement.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively minimizes fin loss during annealing, ensures high-quality SiGe and SiP region growth, reduces parasitic capacitance, and improves device speed by using a self-aligned process that maintains compatibility with current tools and avoids thermal annealing.

Implementation Method 1

The method for depositing the thin oxide layer covering the upper surface of the substrate and sidewalls of the plurality of fin structures in step 2 comprises atomic layer deposition or in-situ steam generation.

Methodology Applied

Scientific EffectAtomic layer deposition: Physical Vapour Deposition

Implementation Method 2

Methodology Applied

Scientific EffectIn-situ steam generation: Evaporation

Implementation Method 3

The method for depositing the oxide dielectric layer in step 3 comprises fluid chemical vapor deposition.

Methodology Applied

Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Implementation Method 4

affecting the subsequent SiGe (silicon germanium) and SiP (silicon phosphate) epitaxial growth

Methodology Applied

Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS11244865B1Method for making self-aligned post-cut SDB FinFET device

Publication Date: 2022.02.08 SHANGHAI HUALI INTEGRATED CIRCUIT CORP

AI summary

The disclosure includes forming a SiGe region on two adjacent fin structures and a SiP region on the fin structures adjacent to the SiGe region; forming SDB trenches; forming SiN plugs over the SDB trenches to make top-sealed hollow SDB trenches. The process for forming SDB trenches adds no additional cost, and the process is compatible with existing process flow. The SiN plugs are configured to seal the SDB trenches from top, such that the SDB trenches are filled with air and do not need to be thermally annealed. The advantage includes low fin loss in the annealing oxidation process and better controlled uniformity of the SDB trenches. Air in the SDB trenches reduces the parasitic capacitance of adjacent contacts, therefore and it is conducive to improving the device speed.