Single Diffusion Break Structure Under Gate Line for FinFET

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Solution Overview

Problem

Current FinFET fabrication methods face challenges in integrating single diffusion break (SDB) structures with metal gate fabrication, which affects the control of the channel region and current between the source and drain in three-dimensional transistor technology.

Innovation Solution

A method involving the formation of a first active region and a second active region on a substrate, with a first single diffusion break structure extending between them, and a gate line intersecting these regions, where the SDB structure is directly under the gate line, using processes such as sidewall image transfer and chemical vapor deposition to create fin-shaped structures and shallow trench isolation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If shallow trench isolation is formed around the fin-shaped structure and STI is removed to form a trench for SDB structure, then the channel region control is improved, but the integration with metal gate fabrication becomes complex and problematic

Engineering Contradiction:
Improvechannel region controlVSAvoidintegration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the SDB structure formation with the metal gate fabrication process by forming the SDB structure directly under the gate line in a integrated manner. The gate line is formed extending along the second direction intersecting the active regions, with the SDB structure positioned directly beneath it, combining two previously separate fabrication sequences into one cohesive process flow.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The SDB structure is formed preliminarily before the gate line is deposited, allowing the gate line to be formed directly over the SDB structure. This preliminary positioning of the SDB structure under the gate line simplifies subsequent processing steps and integrates the isolation function with the gate fabrication process.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If three-dimensional FinFET structure is used to increase overlapping area, then the channel region control is enhanced, but the fabrication integration with SDB structure becomes problematic

Engineering Contradiction:
Improvechannel region controlVSAvoidfabrication integration
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies local quality by positioning the SDB structure specifically under the gate line in the region where it is most needed for channel control, while maintaining the three-dimensional FinFET structure in the active regions. This localized placement of the SDB structure optimizes channel control without complicating the overall fabrication process.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent utilizes the vertical dimension by forming the SDB structure directly under the gate line, creating a three-dimensional arrangement where the SDB structure is positioned beneath the gate line which itself is above the FinFET structure. This vertical stacking approach enhances channel control while maintaining fabrication simplicity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10256155B1Method for fabricating single diffusion break structure directly under a gate line
Publication Date: 2019.04.09 MARLIN SEMICON LTD
  • US10256155B1 patent drawing
  • US10256155B1 patent drawing
  • US10256155B1 patent drawing

AI summary

A method for fabricating semiconductor device includes the steps of: forming a first active region and a second active region extending along a first direction on a substrate; forming a first single diffusion break (SDB) structure extending along a second direction between the first active region and the second active region; and forming a first gate line extending along the second direction intersecting the first active region and the second active region. Preferably, the first SDB structure is directly under the first gate line between the first active region and the second active region.