SDF Manager Hardware Circuit for Task Scheduling
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Solution Overview
Problem
Existing synchronous data flow (SDF) systems face challenges in efficiently identifying and scheduling tasks for execution, leading to excessive overhead, especially in multi-core digital signal processing applications.
Innovation Solution
The implementation of a SDF Manager that supports node identification requests, allowing for explicit identification of the next qualified node for execution, and utilizing hardware acceleration to improve scheduling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional software-based task identification and scheduling is used in SDF systems, then system flexibility and programmability are maintained, but scheduling overhead increases significantly and productivity decreases
Solution Approach 1:
The patent replaces software-based task identification and scheduling mechanisms with hardware-based SDF circuitry. The SDF circuit includes qualification logic that hardware-determines task readiness by monitoring token availability in FIFO buffers, and an identifier register that hardware-maintains the identifier of the next qualified task. This mechanical/hardware substitution eliminates software polling overhead and accelerates task identification to hardware-speed operations.
Solution Approach 2:
The SDF circuit performs self-service by autonomously monitoring its own input FIFO buffers for token availability and automatically updating the task identifier register when qualification conditions are met. The circuit does not require external software intervention to determine task readiness, as it continuously self-evaluates its own state and self-updates the identifier of the next executable task, reducing the burden on external scheduling software.
2Productivity
If hardware acceleration is implemented for task identification, then scheduling efficiency and productivity improve, but device complexity increases
Solution Approach 1:
The SDF circuit is segmented into distinct functional modules: qualification logic that evaluates token availability conditions, an identifier register that stores task identifiers, and interface logic that communicates with external processors. This segmentation allows each module to perform its specific function efficiently while maintaining overall system manageability and reducing the complexity burden of hardware acceleration.
Solution Approach 2:
The SDF circuit is designed with universal functionality to support multiple tasks and multiple FIFO buffers through a single standardized hardware structure. The qualification logic and identifier register can be applied to any task in the SDF graph, and the circuit can monitor multiple input channels simultaneously, reducing the need for separate dedicated hardware for each task and thereby managing complexity.
3Measurement precision
If continuous monitoring of all tasks is performed to identify executable tasks, then scheduling accuracy is maintained, but power consumption increases
Solution Approach 1:
The SDF circuit employs periodic action by only actively evaluating task qualification when relevant events occur, such as when tokens are produced in the FIFO buffers or when the system state changes. Rather than continuously monitoring all tasks at all times, the qualification logic activates periodically based on event triggers, maintaining accurate task readiness detection while reducing power consumption during idle periods when no state changes occur.
Data Source
AI summary
Techniques and mechanisms for identifying a next task to be executed for an application which is modeled with a synchronous data flow (SDF) graph. In an embodiment, the SDF graph comprises nodes which each represent a different respective task, wherein the nodes variously exchange, via channels, tokens which represent data for operations of the application. A manager circuit manages and provides access to schedule registers which provide state information at a node-specific level of granularity. For a given node, a corresponding schedule register provides a status parameter which identifies whether the given node is currently qualified to be executed. The status parameter is based on one or more channel registers which each provide state information at a channel-specific level of granularity. In another embodiment, a processor comprises circuitry to send to the manager circuit a request to identify, based on the schedule registers, a next task to be executed.