SDFQ Multiplexer Channel Sizing to Prevent Scan Race Conditions
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Solution Overview
Problem
In semiconductor devices, scan flip-flops face a race condition during scan/test operations due to mismatched signal propagation delays between data and scan groups, leading to potential misinterpretation of logical states and incorrect latching.
Innovation Solution
Configuring transistors in the scan group with a smaller channel size compared to the data group creates a choke, ensuring slower signal propagation during scan/test operations, thereby emulating the propagation delay of combinational logic and avoiding race conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors in the scan group are configured with the same channel size as the data group, then the device structure is simple and manufacturing is easy, but signal propagation delays are mismatched causing race conditions during scan/test operations
Solution Approach 1:
The patent applies local quality by configuring transistors in the scan group with a first channel size while data group transistors use a second channel size. This localized differentiation in transistor dimensions creates the necessary propagation delay mismatch prevention without requiring complete redesign of all transistors, thus improving reliability while limiting complexity increase to specific regions only.
Solution Approach 2:
The patent changes the physical parameter of transistor channel size to control signal propagation characteristics. By adjusting the channel size parameter of scan group transistors relative to data group transistors, the propagation delay is tuned to match between groups, preventing race conditions. This parameter-based approach provides a straightforward method to resolve the timing contradiction.
2Reliability
If transistors in the scan group are configured with a smaller channel size to create a choke, then race conditions are prevented, but the device area increases and manufacturing complexity increases
Solution Approach 1:
The choke structure is implemented locally within the scan group transistor region rather than throughout the entire device. This localized implementation of smaller channel size transistors creates the necessary propagation delay effect while confining the area impact to specific scan group locations, thus preventing race conditions with minimal overall device area penalty.
Solution Approach 2:
The patent introduces asymmetry in transistor channel sizes between scan and data groups, with scan group transistors having smaller channels to create chokes. This asymmetric configuration is necessary to establish the propagation delay differential that prevents race conditions. The asymmetry is strategically applied only where needed for timing control rather than uniformly across all transistors.
3Reliability
If transistors in the scan group are configured with a smaller channel size, then signal propagation is slowed to emulate combinational logic delay, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes parameter changes in transistor channel size as a design variable to control propagation delay characteristics. By establishing specific channel size relationships between scan and data group transistors, the desired delay emulation is achieved. The manufacturing precision challenge is managed by treating channel size as a controllable parameter within standard fabrication capabilities rather than requiring ultra-precise control.
Data Source
AI summary
A semiconductor device has a cell region including active regions that extend in a first direction and in which are formed components of transistors. The transistors of the cell region are arranged to function as a scan insertion D flip flop (SDFQ). The SDFQ includes a multiplexer serially connected at an internal node to a D flip-flop (FF). The transistors of the multiplexer include data transistors for selecting a data input signal, the data transistors having a first channel configuration with a first channel size, and scan transistors of the multiplexer for selecting a scan input signal, the scan transistors having a second channel configuration with a second channel size. The second channel size is smaller than the first channel size.