SDFQ Multiplexer with Smaller Scan Transistors for Race-Free Timing
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Solution Overview
Problem
In semiconductor devices, scan flip-flops face a race condition during scan/test operations due to mismatched signal propagation delays between data and scan groups, leading to potential misinterpretation of logical states and incorrect latching.
Innovation Solution
Configuring transistors in the scan group with a smaller channel size compared to the data group creates a choke effect, ensuring slower signal propagation during scan/test operations, thereby emulating the propagation delay of combinational logic and avoiding race conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors in the scan group are configured with the same channel size as the data group, then the device structure is simple and manufacturing is easy, but signal propagation delays are mismatched causing race conditions during scan/test operations
Solution Approach 1:
The patent applies local quality by configuring transistors in the scan group with a first channel size while data group transistors have a second channel size. This differential configuration creates the necessary propagation delay mismatch locally in the scan path without affecting the entire device, thereby preventing race conditions during scan/test operations while maintaining overall structural simplicity.
2Reliability
If transistors in the scan group are configured with a smaller channel size to create choke effect, then signal propagation delay is extended to prevent race conditions, but the transistor channel dimensions are reduced
Solution Approach 1:
The patent applies parameter changes by modifying the channel size parameter of transistors in the scan group to be smaller than those in the data group. This parameter adjustment creates the choke effect that extends signal propagation delay in the scan path, preventing race conditions during scan/test operations while maintaining appropriate timing characteristics.
3Manufacturing precision
If all transistors have the same channel size, then manufacturing precision requirements are simplified, but signal propagation delays cannot be differentiated between data and scan paths
Solution Approach 1:
The patent applies local quality by implementing different channel sizes for scan group transistors versus data group transistors. This localized differentiation allows precise control of signal timing in the scan path while maintaining uniform manufacturing processes, as the dimension difference is built into the design rather than requiring post-manufacturing adjustment.
Data Source
AI summary
A semiconductor device includes first active regions extending in a first direction and having a first number of fins; second active regions extending in the first direction and having a second number of fins, the second number of fins being less than the first number of fins; data transistors formed at least in part in the first active regions; and scan transistors formed at least in part in the second active regions. The data transistors and the scan transistors are included in a scan insertion D flip-flop (SDFQ) that includes a multiplexer serially connected at an internal node to a D flip-flop (FF), the multiplexer including the data transistors for selecting a data input signal, and including the scan transistors for selecting a scan input signal.