Bit Sequence Detector for SDI Timing Reference Signals
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Solution Overview
Problem
Existing SDI receivers require significant logic resources to detect timing reference signals, which can be insufficient in FPGAs, especially for multi-rate decoders handling both SD-SDI and HD-SDI data streams, limiting the availability of logic resources for other video processing functions.
Innovation Solution
A method and apparatus using three dual-port synchronous memories to process bit-patterns, generate codes, and detect bit sequences within a data stream, reducing the logic required for pattern matching by employing a bit sequence detector that processes pairs of codes and generates detection data, allowing for efficient detection of timing reference signals in SDI data streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional pattern matching circuits are used to detect timing reference signals, then detection accuracy is maintained, but logic resource consumption increases significantly
Solution Approach 1:
The patent segments the timing reference signal detection into multiple smaller components: a first pattern matching circuit that processes pairs of bit-patterns to generate codes, a second pattern matching circuit that processes pairs of codes to generate combination codes, and a sequence detector that processes sequences of combination codes. This segmentation divides the complex detection task into manageable parts, reducing the logic resources required for each individual circuit while maintaining overall detection accuracy.
Solution Approach 2:
The patent transforms the detection problem from direct bit-pattern matching to a multi-dimensional approach by introducing intermediate code representations. Instead of directly comparing the entire timing reference signal pattern, the system first converts bit-patterns to codes, then codes to combination codes, and finally detects sequences of combination codes. This dimensional transformation reduces the complexity of each matching stage.
2Adaptability or versatility
If multiple SDI receivers are implemented in an FPGA, then processing capability for multi-rate video streams is improved, but available logic resources become insufficient
Solution Approach 1:
By segmenting the pattern matching function into multiple specialized circuits that process different levels of abstraction (bit-patterns → codes → combination codes → sequences), the patent enables parallel implementation of multiple SDI receivers. Each receiver can use its own segmented detection circuitry, allowing multi-rate video stream processing while managing logic resource consumption through efficient circuit partitioning.
Solution Approach 2:
The segmented pattern matching circuits and sequence detector form a universal detection architecture that can handle both SD-SDI and HD-SDI timing reference signals. This multi-functional design allows a single receiver implementation to process different video standards, increasing adaptability without requiring separate dedicated circuits for each standard.
Data Source
AI summary
Method and apparatus for detecting a bit sequence in a data stream is described. In one example, a first memory is configured to process pairs of bit-patterns in the data stream to provide respective pairs of codes from a code table stored in said first memory. A second memory is configured to process pairs of codes from the first memory to provide combination codes from a combination code table stored in the second memory. A third memory is configured to generate detection data in response to a sequence of the combination codes output from the second memory. The first, second, and third memories may be dual-port synchronous memories, such as block random access memory embedded in an integrated circuit. The data stream may be a serial digital interface (SDI) data stream and the bit sequence may be a timing reference signal.