SDIO Bus Clock Power Management in Portable Terminals

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Solution Overview

Problem

Portable terminals experience high power consumption and reduced operating time due to a fixed clock in bus interfaces, which is inefficient for varying application throughputs.

Innovation Solution

A method and apparatus that control the operation clock of the SDIO bus in portable terminals by determining the required throughput for application programs and selectively adjusting the supply voltage, optimizing power management to minimize power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the bus clock is fixed at maximum clock to achieve maximum throughput, then the data transmission speed is improved, but the power consumption increases

Engineering Contradiction:
ImprovethroughputVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic clock frequency adjustment for the SDIO bus interface, transitioning from a fixed maximum clock to a variable clock that adapts to application requirements. The power controller dynamically changes the bus clock frequency based on the throughput needed by running applications, allowing the system to operate at lower frequencies for low-throughput applications and higher frequencies for high-throughput applications, thus resolving the contradiction between maintaining high productivity and reducing energy consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameters of the bus interface by adjusting the clock frequency based on application throughput requirements. The power controller monitors the throughput needs of running applications and modifies the bus clock frequency parameter accordingly, enabling the system to optimize the balance between data transmission speed and power consumption by varying this key parameter rather than maintaining a fixed value.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the bus clock is fixed at maximum clock, then the data transmission capability is improved, but the operating time of the portable terminal is reduced

Engineering Contradiction:
Improvedata transmission capabilityVSAvoidoperating time
Core Design Contradiction:
ProductivityVSDuration of action of moving object

Solution Approach 1:

The patent implements dynamic clock frequency adjustment for the SDIO bus interface, transitioning from a fixed maximum clock to a variable clock that adapts to application requirements. The power controller dynamically changes the bus clock frequency based on the throughput needed by running applications, allowing the system to operate at lower frequencies for low-throughput applications and higher frequencies for high-throughput applications, thus resolving the contradiction between maintaining high productivity and reducing energy consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameters of the bus interface by adjusting the clock frequency based on application throughput requirements. The power controller monitors the throughput needs of running applications and modifies the bus clock frequency parameter accordingly, enabling the system to optimize the balance between data transmission speed and power consumption by varying this key parameter rather than maintaining a fixed value.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8370662B2Apparatus and method for power saving of bus interface in portable terminal
Publication Date: 2013.02.05 ADEIA MEDIA HOLDINGS INC
  • US8370662B2 patent drawing
  • US8370662B2 patent drawing
  • US8370662B2 patent drawing

AI summary

An apparatus and a method for power saving in a portable terminal are provided. The method for power saving in the portable terminal includes determining a throughput when processed by a bus, determining a throughput required for a program and selectively controlling a bus clock connected with a modem according to the determined throughput.