SDIO Packet Controller Superframe Concatenation

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Solution Overview

Problem

The existing SDIO interface experiences high latency and low throughput due to inefficient interrupt handling and polling mechanisms, particularly when dealing with slow IO operations and multiple packet transfers, which is burdensome for applications involving wireless data access and GPS navigation.

Innovation Solution

Implementing a packet controller within the SDIO slave device that concatenates multiple packets into 'superframes' and generates a single interrupt to the host, allowing for efficient data transfer by reducing the number of interrupts and software events, thereby minimizing latency and maximizing throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the master polls the slave device periodically to check for events, then the slave device can notify the master of event completion, but the master processing overhead increases and events may be pending for longer times

Engineering Contradiction:
Improveevent notification reliabilityVSAvoidmaster processing throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent combines multiple individual packet transfer operations into a single superframe transfer operation. Instead of handling each packet separately with individual interrupts and software events, the slave device concatenates multiple packets into a superframe structure that can be transferred in one operation, reducing the number of interrupt handling cycles and software events required.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The slave device performs preliminary actions by pre-concatenating multiple packets into a superframe before the host initiates the transfer. The superframe descriptor is prepared in advance with all necessary packet length information, allowing the host to read multiple packets in a single operation without repeated interrupt handling overhead.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If multiple interrupts are generated for multiple packets, then each packet can be transferred individually, but the response latency increases and throughput decreases

Engineering Contradiction:
Improvedata transfer throughputVSAvoidinterrupt response latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent merges multiple packet transfer operations into a single superframe transfer. The slave device generates a single interrupt for the entire superframe rather than separate interrupts for each packet, reducing interrupt response latency and allowing the host to read multiple packets in one operation, thereby increasing throughput.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The superframe structure enables continuous data transfer by eliminating the interrupt handling overhead between packet transfers. The host can read multiple packets sequentially from the superframe without the processor being tied up in repeated interrupt service routines, maintaining continuous useful action throughout the transfer operation.

Inventive Principle:
Principle #20Continuity of useful action

3Adaptability or versatility

If the slave device uses slow IO operations for complex processing, then functional versatility is improved, but the data transfer latency increases

Engineering Contradiction:
Improvefunctional processing capabilityVSAvoidIO operation latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The slave device performs complex processing and data preparation in advance, storing processed data in its internal memory before the host needs it. The superframe descriptor is prepared beforehand with all packet length information, allowing the host to retrieve pre-processed data without waiting for slow IO operations during the transfer phase.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The slave device acts as an intermediary that performs complex processing locally and buffers results in internal memory. This allows the host to retrieve pre-processed data through fast SDIO transfers without being blocked by the slave's slow IO operations, effectively decoupling processing latency from transfer latency.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8051222B2Concatenating secure digital input output (SDIO) interface
Publication Date: 2011.11.01 SILICON LABORATORIES INC
  • US8051222B2 patent drawing
  • US8051222B2 patent drawing
  • US8051222B2 patent drawing

AI summary

An apparatus and a process for transferring packet data includes receiving packets from a first interface such as a network interface and transferring data to a second interface such as an SD Bus interface such as SDIO using a protocol such as one described in SDCard.org. The SD Bus second interface operates as a slave device to a master device, and the packet transfer from first interface to second interface includes concatenating length fields and packet data fields from packets received on the first interface to form a superframe which is provided to the second interface at time of data transfer. The formation of each superframe includes starting a timer such that the superframe is transmitted to the second interface by asserting an interrupt on that interface when either the timer expires, the number of packet from the first interface exceeds a threshold, or the amount of data from the first interface exceeds a threshold.