SDM Overload Detector Circuit for Faster Signal Fault Detection
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Solution Overview
Problem
Existing ADCs face challenges in quickly and accurately detecting small variations in electrical signals, leading to increased latency, error detection time, and reduced responsiveness in systems that rely on them, particularly in touch-sensing devices and functional safety systems.
Innovation Solution
An SDM overload detector circuit that monitors the output of a sigma-delta modulator to detect overload conditions by comparing consecutive signal values, incrementing a count value when matches occur, and generating an indication when the count exceeds a threshold, allowing for faster detection of overload conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional ADCs are used to detect small variations in electrical signals, then measurement precision can be maintained, but detection time increases and system responsiveness decreases
Solution Approach 1:
The patent segments the detection function into two parallel paths: a conventional ADC path for precise measurement and a new SDM-based path for fast overload detection. The SDM independently processes the input signal to detect overload conditions without waiting for the conventional ADC to complete its conversion, thereby reducing detection time while maintaining measurement precision through the conventional ADC.
Solution Approach 2:
The SDM performs preliminary detection of overload conditions by monitoring the input signal before the conventional ADC completes its conversion process. The SDM's fast response capability allows it to detect overload conditions in advance, generating an early warning that prevents wasted processing time on invalid conversions.
2Measurement precision
If conventional ADCs are used for signal conversion, then accurate data conversion is achieved, but error detection time increases
Solution Approach 1:
The SDM acts as an intermediary detection mechanism that monitors the input signal for overload conditions independently of the conventional ADC conversion process. By introducing this intermediate detection layer, the system can identify errors (overload conditions) faster than the conventional ADC's conversion time, allowing for quicker error detection without compromising conversion accuracy.
3Measurement precision
If conventional ADCs are used in touch-sensing devices, then touch detection accuracy is maintained, but system responsiveness decreases
Solution Approach 1:
The patent segments the touch detection system into two functional components: the conventional ADC for accurate touch coordinate detection and the SDM for rapid overload/disturbance detection. This segmentation allows the system to maintain high touch detection accuracy while improving responsiveness by quickly identifying and flagging overload conditions that would otherwise delay processing.
Solution Approach 2:
The SDM provides fast feedback regarding overload conditions to the control logic, enabling the system to respond more quickly to potential errors. This feedback mechanism allows the touch-sensing device to maintain accuracy by using the conventional ADC for precise measurements while improving responsiveness through the SDM's rapid overload detection and immediate feedback.
4Reliability
If conventional ADCs are used, then functional safety can be ensured, but false detections increase
Solution Approach 1:
The SDM serves as an intermediary verification layer that independently monitors for overload conditions. By cross-checking the SDM's overload detection results against the conventional ADC's conversion results, the system can distinguish between true overload conditions and false detections caused by noise or transient disturbances, thereby maintaining functional safety while reducing false positive rates.
Data Source
AI summary
An overload detector circuit includes first logic circuitry and second logic circuitry. The first logic circuitry to receive a bitstream from a sigma-delta modulator (SDM) of a receiver channel, the first logic circuitry to compare a current bit of the bitstream with a previous bit of the bitstream and output an indication of as match. The second logic circuitry to track a number of consecutive matches in the bitstream and output an indication of a first overload condition responsive to the number of consecutive matches satisfying a first threshold criterion.