SDN Processing Engine Parallel Data Manipulation
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Solution Overview
Problem
Existing SDN processing engines face limitations in flexibility and performance due to prior art ASIC-based designs and 64-bit CPUs, which struggle to meet network bandwidth and latency requirements for processing hundreds of data bytes per cycle, and FPGAs are inadequate for complex network protocols at high throughput.
Innovation Solution
A software-defined networking (SDN) processing engine with a programmable control path and data path, featuring a Control Bits Extractor, Word Comparing Cone, multi-stage MUX/LUT Logic Cone, and Instruction Tables for conditional data manipulation, allowing parallel processing of multiple inputs and outputs at full throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ASIC-based designs are used, then processing speed and throughput are improved, but flexibility and reprogrammability deteriorate
Solution Approach 1:
The patent implements a universal processing engine that can perform multiple network functions (routing, switching, firewall, NAT, etc.) through a single reconfigurable architecture. The engine uses programmable instruction tables and configurable logic cones to adapt to different protocols and processing requirements, eliminating the need for dedicated ASICs for each function while maintaining high throughput performance.
Solution Approach 2:
The processing engine employs dynamic reconfiguration capabilities where instruction tables and logic cone configurations can be modified at runtime to adapt to changing network requirements. This allows the system to transition between different processing modes and protocols without hardware changes, combining the speed of ASIC with the flexibility of software-defined networking.
2Adaptability or versatility
If 64-bit general-purpose CPUs are used, then flexibility is improved, but processing speed and latency performance deteriorate
Solution Approach 1:
The patent replaces traditional general-purpose CPU instruction execution with a specialized processing engine that uses direct hardware-based instruction table lookup and parallel logic cone evaluation. This substitution eliminates the overhead of conventional CPU instruction cycles while maintaining programmability through configurable instruction tables, achieving both high-speed processing and flexibility.
Solution Approach 2:
The processing engine divides data processing into parallel segments handled by multiple logic cones that can simultaneously evaluate different aspects of packet data. This parallel segmentation allows the engine to process hundreds of bytes per cycle by distributing work across multiple independent processing units that operate concurrently.
3Adaptability or versatility
If FPGAs are used, then reconfigurability is improved, but logic cell capacity and interconnect complexity limit throughput performance
Solution Approach 1:
The patent extracts the essential processing functions from complex FPGA architectures into a streamlined engine design that uses simplified instruction tables and direct logic cone implementations. By removing unnecessary FPGA interconnect layers and abstraction overhead, the system achieves higher operating frequencies and throughput while retaining reconfigurability through programmable instruction sets.
Data Source
AI summary
Embodiments of the present invention relate to fast and conditional data modification and generation in a software-defined network (SDN) processing engine. Modification of multiple inputs and generation of multiple outputs can be performed in parallel. A size of each input or output data can be large, such as in hundreds of bytes. The processing engine includes a control path and a data path. The control path generates instructions for modifying inputs and generating new outputs. The data path executes all instructions produced by the control path. The processing engine is typically programmable such that conditions and rules for data modification and generation can be reconfigured depending on network features and protocols supported by the processing engine. The SDN processing engine allows for processing multiple large-size data flows and is efficient in manipulating such data. The SDN processing engine achieves full throughput with multiple back-to-back input and output data flows.