SDR Signal Processing With LUT and SIMD for Fast Viterbi Decoding

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Solution Overview

Problem

Software-defined radio (SDR) systems face challenges in achieving high-speed wireless communication due to decoding errors caused by noise and interference, and existing technologies struggle to implement efficient digital signal processing on general-purpose computing devices.

Innovation Solution

The implementation of a fully programmable SDR platform that uses a combination of hardware and software techniques, including multi-core processor architectures, lookup tables, and Single Instruction Multiple Data (SIMD) extensions, to accelerate wireless protocol processing and support high-throughput, low-latency data transfer, enabling efficient digital signal processing on general-purpose computing devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If software algorithms are used for digital signal processing in SDR, then programmability and flexibility are improved, but processing speed and data rate capability deteriorate

Engineering Contradiction:

ImproveprogrammabilityVSAvoidprocessing speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent replaces traditional software-based signal processing with a hybrid architecture that uses FPGA hardware circuits for time-critical processing functions. This substitution of mechanical/software systems with hardware systems achieves both high speed and programmability through the FPGA's reconfigurable logic elements that can be programmed to implement specific signal processing algorithms in hardware.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent divides the SDR architecture into distinct segments: hardware circuits implemented in FPGA for high-speed processing of time-critical functions (such as modulation/demodulation and error correction), and software components for higher-level protocol processing. This segmentation allows each segment to be optimized for its specific function while working together as an integrated system.

Inventive Principle:

Principle #1Segmentation

2Speed

If hardware circuits are used for digital signal processing, then processing speed is improved, but programmability and flexibility deteriorate

Engineering Contradiction:

Improveprocessing speedVSAvoidprogrammability

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The patent implements a universal processing platform using FPGA technology that can be programmed to support multiple wireless communication standards and protocols. The same hardware platform can be reconfigured through software to implement different modulation schemes, coding rates, and protocol stacks, providing both high-speed hardware processing and full programmability for adapting to different communication requirements.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If error correction decoding is performed to reduce decoding errors, then reliability is improved, but computational complexity and processing time increase

Engineering Contradiction:

Improvedecoding accuracyVSAvoidcomputational complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces complex software-based error correction decoding with hardware-implemented decoding algorithms in the FPGA. This hardware implementation performs sophisticated error correction (such as Viterbi decoding, turbo decoding, or LDPC decoding) at line rates without the overhead of software interpretation, achieving high reliability while maintaining processing speed.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Reliability

If sophisticated error correction algorithms are implemented, then decoding accuracy is improved, but processing time and latency increase

Engineering Contradiction:

Improvedecoding accuracyVSAvoidprocessing time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements error correction decoding in hardware circuits within the FPGA, enabling parallel processing of multiple data streams simultaneously. This hardware implementation executes decoding algorithms in deterministic time intervals at line rate, eliminating the variable processing times associated with software execution and ensuring that sophisticated error correction does not introduce unacceptable latency.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS8627189B2High performance digital signal processing in software radios

Publication Date: 2014.01.07 MICROSOFT TECHNOLOGY LICENSING LLC

AI summary

An extensive use of look-up table (LUT) and single instruction multiple data (SIMD) in different algorithms in a software-defined radio (SDR) system is described. In particular, the LUT is used during spreading modulation, mapping and spreading, scrambling, de-scrambling, soft demapping, and the like. The SIMD is executed by a multi-core processor during implementation of a “min” operation to find an optimal path in a Trellis diagram for a Viterbi decoder.