SDRAM Address Mapping for Skew Correction
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Solution Overview
Problem
Existing memory control systems face inefficiencies in correcting skew and bow in image data transmission due to mechanical and assembly inaccuracies, leading to increased processing time and overhead when shifting pixel positions in the sub-scanning direction.
Innovation Solution
A memory control device with an address mapping unit that assigns main scanning and sub-scanning addresses to column, row, and bank addresses in an SDRAM, allowing for successive burst transfers while changing the sub-scanning address at the end of each transfer, and setting the burst size based on the minimum number of successive pixels shifted during correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sub-scanning address is changed during burst transfer to correct skew and bow, then image correction precision is improved, but processing time increases due to precharge overhead
Solution Approach 1:
The image data is divided into multiple banks (Bank 0, Bank 1, Bank 2, Bank 3) based on the main scanning address. By segmenting the data across multiple banks, the system can switch between banks during burst transfer without requiring precharge operations, enabling sub-scanning address changes for skew and bow correction while maintaining high-speed processing.
Solution Approach 2:
The patent implements dynamic bank switching during the burst transfer process. The memory controller dynamically selects which bank to access based on the main scanning address, allowing continuous data transfer across bank boundaries without interrupting the burst sequence. This dynamic approach eliminates static precharge requirements and enables real-time correction of skew and bow.
2Measurement precision
If the burst length is shortened to accommodate precise skew and bow correction, then correction precision is improved, but memory access performance deteriorates
Solution Approach 1:
The patent introduces a new dimension of bank addressing perpendicular to the traditional row-column address space. By utilizing the bank dimension (Bank 0-3) in conjunction with row and column addresses, the system can maintain long burst lengths for high performance while simultaneously achieving precise pixel position adjustments for skew and bow correction through coordinated bank switching.
Data Source
AI summary
Disclosed is a memory control device, including: an address mapping unit configured to assign a main scanning address and a sub-scanning address to a column address, a row address and a bank address of an SDRAM, to assign lower N bit(s) (N is a positive integer) for indicating an address corresponding to a burst size of a burst transfer among the main scanning address, to lower bit(s) of the column address, and to assign predetermined number of bit(s) arranged successively to an upper bit side of the lower N bit(s) among the main scanning address, to the bank address; and an access executing unit configured to read or write one line of image data in the main scanning direction by carrying out the burst transfer successively multiple times in a multibank operation while the sub-scanning address is changed at an end of the burst transfer.