SDRAM Addressing Method for High Capacity Memory Without Pin Cost
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Solution Overview
Problem
Current DDR4 SDRAM memory technologies are limited in capacity due to the pin usage and addressing scheme, which restricts memory modules to 256 GB per DIMM, and increasing pin count or cost is undesirable.
Innovation Solution
The proposed solution involves extending existing commands like ACT and RD/WR with additional cycles to carry more address bits, repurposing unused address bits for extended addressing, and modifying timing parameters to support back-to-back commands, allowing for increased row and column addressability without adding pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the current pin usage and addressing scheme is used, then the memory module supports up to 256 GB per DIMM, but memory capacity larger than 256 GB is not supported
Solution Approach 1:
The row address bits are segmented into two subsets: a first subset specified in the row address command and a second subset specified in a subsequent column address command. This segmentation allows the memory device to receive and process more row address bits than the standard architecture would normally permit, thereby enabling addressing of larger memory capacities without adding physical pins.
Solution Approach 2:
The column address command is given dual functionality: it serves both as the standard column address command and as a vehicle to carry additional row address bits (the second subset). This multi-functionality allows the existing pin infrastructure to support extended addressing capabilities, enabling high-capacity memory without increasing pin count.
2Quantity of substance
If additional pins are added to support high capacity memory, then addressability beyond 256 GB is enabled, but pin cost and pin count increase
Solution Approach 1:
The column address command pins are made multi-functional by allowing them to carry both column address information and additional row address bits. This eliminates the need for separate dedicated pins for extended addressing, maintaining the same pin count while achieving high-capacity memory support.
Solution Approach 2:
The addressing parameters are changed by extending the number of row address bits beyond the standard limit. Instead of adding physical pins, the system changes the addressing protocol to utilize existing pins more efficiently, thereby increasing memory capacity without increasing device complexity.
3Quantity of substance
If row address bits are increased beyond the standard architecture, then higher memory capacity is addressed, but the standard row address command cannot accommodate all bits
Solution Approach 1:
The extended row address is segmented across two commands: the first subset of row address bits is provided in the standard row address command, and the second subset is provided in the subsequent column address command. This segmentation maintains compatibility with standard protocols while enabling extended addressing capability.
Solution Approach 2:
The row address is preliminarily established in the row address command with the first subset of bits, and then completed with the second subset in the column address command. This preliminary action allows the memory device to begin processing the row address early while still receiving the complete extended address information.
Data Source
AI summary
A method for addressing memory device data arranged in rows and columns indexed by a first number of row address bits and a second number of column address bits, and addressed by a row command specifying a third number of row address bits followed by a column command specifying a fourth number of column address bits, the first number being greater than the third number or the second number being greater than the fourth number, includes: splitting the first number of row address bits into first and second subsets, and specifying the first subset in the row command and the second subset in a next address command when the first number is greater than the third number; otherwise splitting the second number of column address bits into third and fourth subsets, and specifying the fourth subset in the column command and the third subset in a previous address command.