SDRAM Controller Partition Using Source Synchronous Clocking
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Solution Overview
Problem
Integrated circuits, particularly field programmable gate arrays (FPGAs), face challenges with timing skew and latency in communication due to mismatches in distances between memory controllers and input/output (IO) banks, exacerbated by system synchronous communication. Additionally, disaggregation of memory controllers to older technology nodes increases power, performance, and area costs, and introduces latency.
Innovation Solution
The system is modified to use an independent source synchronous memory controller with separate clocks for transmit and receive channels, keeping the memory controller on the main FPGA die and communicating with physical layers and IOs on older technology nodes in a source synchronous manner, allowing for realignment of signals through existing re-alignment circuitry to reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If system synchronous communication is used with a common clock, then communication simplicity is maintained, but timing skew between different IO paths increases
Solution Approach 1:
The patent changes the clocking parameter from a shared system synchronous clock to independent source synchronous clocks for each data path. Each lane has its own clock that is launched with the data, changing the temporal parameter of clock distribution to eliminate skew accumulation across different path lengths.
Solution Approach 2:
The patent introduces an intermediary clock signal that travels with the data along each path. Instead of using a distant common clock as mediator, each data path has its own clock mediator that is launched from the source, ensuring synchronized arrival of data and clock edges despite path length variations.
2Ease of manufacture
If the memory controller is disaggregated to older technology nodes, then manufacturing cost is reduced, but power consumption and latency increase
Solution Approach 1:
The patent segments the memory controller into separate transmit and receive channels, each operating independently with its own clock. This segmentation allows each channel to be optimized separately and reduces the overall power consumption compared to a monolithic controller, while enabling placement on cost-effective technology nodes.
Solution Approach 2:
The patent introduces dynamic clock management where clocks are selectively enabled and disabled based on operational mode (transmit or receive). This dynamic approach reduces power consumption by eliminating idle clocking activity, allowing the controller to scale power usage with actual workload rather than maintaining full power readiness.
3Ease of manufacture
If the memory controller is disaggregated to separate chiplets, then yield and manufacturing flexibility improve, but communication latency increases
Solution Approach 1:
The patent performs preliminary action by launching the clock signal simultaneously with the data signal at the source. This pre-synchronization ensures that the clock and data arrive together at the destination without requiring additional latency for clock alignment or phase adjustment at the receiving end.
Solution Approach 2:
The patent replaces the mechanical/physical constraint of synchronized clock distribution across chiplets with an electrical solution where independent clocks are launched with each data transaction. This substitution eliminates the need for complex inter-chiplet clock synchronization infrastructure, reducing latency while maintaining manufacturing flexibility.
4Adaptability or versatility
If path lengths from memory controller to different IOs are mismatched, then IO bank flexibility is improved, but timing skew is exacerbated
Solution Approach 1:
The patent changes the fundamental parameter of clock distribution from a fixed system-wide clock to dynamic per-lane clocks. This parameter change allows each IO path to have its own timing reference, accommodating varying path lengths and IO bank locations without compromising timing precision, thereby enabling greater IO bank flexibility.
Data Source
AI summary
Systems or methods of the present disclosure may provide a programmable logic fabric and a memory controller communicatively coupled to the programmable logic fabric. The systems or methods also include a physical layer and IO circuit coupled to the programmable logic fabric via the memory controller and a FIFO to receive read data from a memory device coupled to the physical layer and IO circuit. Furthermore, the FIFO is closer to the memory controller than to the physical layer and IO circuit.