SDRAM DLL Lock Recovery Using Reset and Rough Delay Updates
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Solution Overview
Problem
Conventional DLL circuits in semiconductor memory devices take a long time to recover the locking state after it is broken due to external changes such as changes in clock frequency (tCK) or power supply voltage (VDD), as they perform phase updates with a small delay amount.
Innovation Solution
A DLL circuit with a control unit that generates a reset signal and conducts phase updates using a rough delay value when a significant delay difference is detected between the internal clock signal and the feedback clock signal, allowing for faster recovery of the locking state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DLL circuits perform phase updates with a small delay amount under locking state, then the locking state stability is maintained, but the recovery time when locking state is broken becomes excessively long
Solution Approach 1:
The patent applies dynamics by making the delay amount adjustable based on the locking state. When the locking state is broken (detected by the reset signal), the system dynamically switches to a larger delay amount for faster phase updates. When locked, it uses a smaller delay amount for stability. This dynamic adjustment resolves the contradiction between stability and recovery speed.
Solution Approach 2:
The patent changes the delay parameter based on the operational state. The delay amount is not fixed but varies between two states: a larger delay value when breaking lock (for fast recovery) and a smaller delay value when locked (for stability). This parameter change enables the system to optimize performance for different operational conditions.
2Speed
If DLL circuits use a larger delay amount for phase updates, then the recovery speed improves, but the locking state stability deteriorates
Solution Approach 1:
The system dynamically adjusts the delay amount based on the locking state detected by the phase comparator and control logic. During lock acquisition, a larger delay amount is used for fast convergence. Once locked, the system switches to a smaller delay amount to maintain stability, thus avoiding the trade-off of using a fixed large delay value.
Solution Approach 2:
The patent implements periodic monitoring of the locking state through the phase comparator, which continuously compares the internal clock signal with the feedback clock signal. Based on this periodic detection, the system periodically adjusts the delay amount, switching between large and small values according to whether the locking state is maintained or broken.
3Measurement precision
If DLL circuits continuously monitor phase difference with high precision, then the locking state detection accuracy improves, but the circuit complexity increases
Solution Approach 1:
The patent extracts only the essential function needed for locking state detection: comparing the phases of the internal clock signal and feedback clock signal. The phase comparator outputs a simple logical signal indicating whether the locking state is maintained or broken, without requiring complex continuous measurement of phase difference magnitude. This extraction of essential function reduces circuit complexity while maintaining sufficient detection accuracy.
Solution Approach 2:
The patent uses a simple phase comparator that generates a reset signal when locking state is broken, rather than employing complex continuous phase measurement circuits. The monitoring is performed only when necessary (when locking state may be broken), using minimal circuitry. This approach achieves sufficient detection accuracy with minimal circuit complexity.
Data Source
AI summary
A delay locked loop (DLL) circuit for a synchronous dynamic random access memory (SDRAM) is provided. If a locking state is broken due to an external change such as a change of tCK or power supply voltage, indicating that a delay of a delay replication modeling unit involved in a DRAM is abruptly changed, the locking state can be recovered within a certain time, e.g., 200 tCK, by creating an internal reset signal in the DLL circuit by a circuit that monitors the state and then conducting a phase update using a rough delay value.