SDRAM Interface Feedback Clock Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing data interface devices for SDRAM face challenges in synchronizing the phase between the internal clock and data, leading to delays and potential setup or hold violations, which necessitate lowering the operating frequency and complicate the design of DLL circuits.
Innovation Solution
A data interface device using a board clock and selective data capturing, with feedback clock synchronization to match the data input/output timing with the internal clock, eliminating the need for an internal DLL circuit by employing a register part with double flip-flops and AND elements to manage phase differences and generate feedback clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a DLL circuit is used to synchronize internal clock and board clock, then phase matching between internal clock and data is improved, but device complexity increases
Solution Approach 1:
The patent extracts the phase matching function from a complex DLL circuit and implements it using simpler components: a register part with double flip-flops and AND elements. This separates the synchronization function from the full DLL system, reducing complexity while maintaining reliability.
Solution Approach 2:
The patent introduces a feedback clock as an intermediary signal that mediates between the internal clock and board clock. The feedback clock is generated by passing the internal clock through a sequential path (output pad, memory, input pad) and feeding it back to the register part, where it interacts with the board clock to achieve phase matching without requiring a full DLL circuit.
2Reliability
If operating frequency is lowered to prevent setup or hold violations, then reliability of data input is improved, but productivity decreases
Solution Approach 1:
The patent implements dynamic phase adjustment through the feedback clock mechanism. The system automatically adapts the timing relationship between internal clock and data based on actual delay conditions, allowing the operating frequency to be optimized without causing setup or hold violations. This dynamic adjustment eliminates the need to lower frequency as a safety measure.
3Reliability
If negative edge of internal clock is used to prevent setup or hold violation, then reliability of data input is improved, but phase matching precision deteriorates
Solution Approach 1:
The patent uses feedback from the board clock (passed through the sequential path) to the register part to continuously adjust and match phases. This feedback mechanism allows precise phase alignment to be maintained, replacing the coarse negative edge triggering with a fine-grained feedback-controlled synchronization system that achieves both reliability and precision.
Data Source
AI summary
The data interface device accesses a memory operating in synchronization with a clock. A board clock and selective data capturing improve the operating rate of a memory interface and time-synchronize data flow from memory to memory controller with a internal clock produced by the memory controller; or time-synchronize data flow from the memory controller with the board clock. The internal clock is passed through a sequential path of an output pad of the memory controller, the memory, and an input pad of the memory controller and then re-inputted into the memory controller thereby the feedback clock is generated. The selective data capturing uses a register part for storing data inputted into the memory controller. The register part for storing the data is configured by double registers that are operated in an alternative manner according to a correlation between the inputted data and the feedback clock.