Dual-Path SDRAM Convolutional Interleaver for Burst Write Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Convolutional interleaving techniques face inefficiencies due to the asymmetry in data throughput caused by sequential-write and non-sequential-read addresses in SRAM, and the high cost and limited bandwidth of SDRAM, which restricts the throughput of convolutional interleavers in data communication systems.
Innovation Solution
Implementing a dual-path convolutional interleaver that uses a small SRAM to sort and buffer data before performing large sequential burst writes to SDRAM, optimizing access by accumulating data for four commutator loops and writing in a staggered pattern to minimize address changes and maximize throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If sequential-write and non-sequential-read addresses are used in SRAM for convolutional interleaving, then data sorting and buffering can be achieved, but data throughput is reduced due to address asymmetry
Solution Approach 1:
The invention divides the interleaver into two separate paths (Path A and Path B), each handling sequential-write operations independently. This segmentation allows the system to maintain sorting functionality while avoiding the throughput penalty of asymmetric address access, as each path can operate optimally with matched read-write sequences.
Solution Approach 2:
The patent introduces SDRAM as an intermediary buffer between the SRAM sorting stage and the output. The SDRAM absorbs the address asymmetry issue by serving as a staging area where data can be temporarily stored and retrieved in an optimized sequence, decoupling the SRAM's sorting function from the throughput-critical data flow.
2Quantity of substance
If SDRAM is used for data buffering in convolutional interleaver, then larger capacity is achieved, but bandwidth is limited and cost increases
Solution Approach 1:
The buffering function is segmented between SRAM and SDRAM, with SRAM handling the high-speed sorting operations and SDRAM providing supplementary capacity. This division allows the system to leverage the high bandwidth of SRAM for critical path operations while using SDRAM only when additional capacity is needed, avoiding the bandwidth limitation of using SDRAM exclusively.
Solution Approach 2:
Data is pre-sorted and buffered in SRAM before being transferred to SDRAM. This preliminary action in the high-performance SRAM ensures that when data moves to the lower-bandwidth SDRAM, it is already organized optimally, maximizing the utilization of SDRAM's limited bandwidth and reducing the impact of its speed constraints.
3Adaptability or versatility
If more address changes occur during burst writing to SDRAM, then data can be written flexibly, but throughput decreases
Solution Approach 1:
The patent implements a periodic bursting pattern where data is accumulated in SRAM until a threshold is reached, then transferred to SDRAM in large sequential bursts. This periodic action minimizes the number of address changes during writing, as each burst operation writes contiguous blocks of data, thereby maximizing throughput while maintaining the flexibility to adapt burst size and frequency to data patterns.
Solution Approach 2:
Data is pre-organized in SRAM in an order that optimizes the subsequent burst write sequence to SDRAM. By performing preliminary sorting and ordering in the high-speed SRAM, the system ensures that when data is transferred to SDRAM, it follows a predictable sequential pattern that minimizes address changes and maximizes the efficiency of burst write operations.
Data Source
AI summary
An SDRAM convolutional interleaver with two paths. Symbols are assigned to a given one of the two paths, then are sorted to minimize (to one) a number of breaks in a sequential Interleaver write address. After sorting, the symbols are stored staggered in SRAM and burst written to SDRAM. Before writing to SDRAM, data is accumulated for four symbols at a time, and the data is written four symbols wide to optimize SDRAM access time. 8 bit symbols are written 32 bits at a time to SDRAM.