SDRAM Timing Measurement Using Phase-Corrected Trigger Signals
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Solution Overview
Problem
Measuring the timing relationship between data signals (DQ) and clock signals (DQS) in SDRAM memory buses is challenging due to phase variations between READ and WRITE operations, leading to jumbled displays on oscilloscopes and the need for expensive additional equipment or expertise to separate signals.
Innovation Solution
Combining control signals from either READ or WRITE operations into a trigger signal for an oscilloscope, while continuously driving DQ and DQS signals during both operations, to clarify the display and enable precise timing measurement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both READ and WRITE operations are captured and displayed on the oscilloscope, then comprehensive timing measurement is achieved, but the display becomes jumbled and difficult to read
Solution Approach 1:
The patent segments the mixed READ and WRITE operation signals into separate display traces by detecting operation type and applying phase correction. The oscilloscope divides the composite signal into distinct READ traces and WRITE traces, each properly phased, allowing comprehensive measurement while maintaining display clarity.
Solution Approach 2:
The patent introduces an intermediary signal processing mechanism that detects the operation type (READ or WRITE) and applies appropriate phase shifting to DQS signals before display. This intermediary processing layer separates the jumbled signals into distinct, readable traces while preserving both operation types for measurement.
2Difficulty of detecting and measuring
If only READ or only WRITE operations are looped for measurement, then the oscilloscope display is clarified, but signal quality issues during bus turn-around time are missed
Solution Approach 1:
The patent implements a dynamic measurement approach where the oscilloscope automatically adapts its trigger and phase reference based on the detected operation type. By dynamically switching between READ and WRITE operation modes and applying appropriate phase corrections, the system maintains display clarity for each operation type while comprehensively capturing both during bus turn-around periods.
Solution Approach 2:
The patent changes the phase parameter of the DQS signal reference based on the detected operation type. When a WRITE operation is detected, the system applies a 180-degree phase shift to the DQS reference, allowing clear display of WRITE-specific timing issues while maintaining ability to detect both operation types during transitions.
3Difficulty of detecting and measuring
If a separate logic analyzer is used to separate signals, then signal separation is achieved, but additional expensive equipment and expertise are required
Solution Approach 1:
The patent makes the oscilloscope multi-functional by integrating operation type detection, phase reference generation, and signal separation capabilities directly into the oscilloscope system. This eliminates the need for separate logic analyzers by giving the oscilloscope the universal ability to handle both timing measurement and signal separation functions.
Solution Approach 2:
The patent implements self-service functionality where the oscilloscope automatically detects operation types from the captured signals and autonomously applies the appropriate phase corrections and trigger settings. The system serves itself by eliminating the need for external logic analyzers or specialized expertise to separate READ and WRITE signals.
Data Source
AI summary
Measuring control signal timing for synchronous dynamic random access memory (‘SDRAM’), including combining into a trigger signal for an oscilloscope display control signals of an SDRAM under test, the control signals derived only from a single type of memory operations; and driving, continually during both READ and WRITE operations to and from the SDRAM under test, the oscilloscope display with a memory bus data signal (‘DQ’) and a memory bus clock signal (‘DQS’) from the SDRAM under test.