Seal Conductor Isolation in Semiconductor Layouts for Higher Withstand Voltage
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Solution Overview
Problem
The existing semiconductor device structure, where the seal conductor is grounded to the semiconductor substrate, leads to undesirable conduction between metal electrodes and the seal conductor when a voltage is applied, resulting in decreased withstand voltage due to electric leakage and discharge.
Innovation Solution
A semiconductor device design with a seal conductor embedded as a wall in the insulating layer, electrically separated from the semiconductor chip and terminals, which demarcates regions and suppresses conduction between the high and low potential terminals and the seal conductor, thereby improving withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the seal conductor is embedded in interlayer insulating layers to surround active elements, then moisture protection and physical sealing are improved, but electric leakage and discharge occur between the seal conductor and high potential electrodes
Solution Approach 1:
Insulating layers are applied to the seal conductor before it is embedded in the interlayer insulating layers. This preliminary insulation treatment ensures that when the seal conductor is positioned to surround active elements and metal electrodes, it already has protective insulation that prevents electric leakage and discharge, while maintaining its moisture barrier function.
Solution Approach 2:
The seal conductor structure is made composite by combining conductive material for ESD protection with insulating material coatings. This composite structure allows the seal conductor to simultaneously provide moisture protection, ESD protection, and electrical isolation from high potential electrodes, eliminating electric leakage while maintaining all protective functions.
Data Source
AI summary
A semiconductor device includes a semiconductor chip that has a main surface, an insulating layer that is formed on the main surface, a functional device that is formed in at least one among the semiconductor chip and the insulating layer, a low potential terminal that is formed on the insulating layer and is electrically connected to the functional device, a high potential terminal that is formed on the insulating layer at an interval from the low potential terminal and is electrically connected to the functional device, and a seal conductor that is embedded as a wall in the insulating layer such as to demarcate a region including the functional device, the low potential terminal and the high potential terminal from another region in plan view, and is electrically separated from the semiconductor chip, the functional device, the low potential terminal and the high potential terminal.