Seal Ring Interconnect Layout to Prevent Corner Cracking
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Solution Overview
Problem
Existing seal rings in semiconductor integrated circuits provide inadequate protection against environmental conditions and dicing processes, leading to moisture degradation, ionic contamination, and potential damage during processing.
Innovation Solution
A seal ring structure is formed around the circuit region, extending vertically from the substrate and comprising a continuous multi-layer interconnect structure that encases the circuit region, with specific configurations to exclude super redistribution layers and redistribution vias from corner regions to mitigate cracking and delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a seal ring structure is formed around the circuit region, then protection against environmental conditions and dicing processes is improved, but device complexity increases
Solution Approach 1:
The seal ring structure is merged with the multi-layer interconnect structure, combining the protective seal ring function with the existing interconnect layers. This integration allows the seal ring to provide environmental protection while utilizing the same fabrication processes and structural framework as the interconnect system, thereby reducing overall device complexity.
Solution Approach 2:
The seal ring structure serves multiple functions: it provides environmental protection, acts as part of the interconnect system, and contributes to the overall structural integrity of the semiconductor device. This multi-functionality reduces the need for separate protective structures, simplifying the overall device design while maintaining reliability.
2Reliability
If a continuous multi-layer interconnect structure is used for the seal ring, then protection against moisture degradation is improved, but manufacturing precision requirements increase
Solution Approach 1:
The seal ring structure is formed concurrently with the multi-layer interconnect structure during the same fabrication process. By performing the seal ring formation as a preliminary action integrated into the interconnect fabrication sequence, the patent avoids the need for separate high-precision alignment steps, thereby reducing manufacturing precision requirements while ensuring continuous coverage for moisture protection.
3Strength
If redistribution layers and vias are excluded from corner regions, then resistance to cracking and delamination is improved, but interconnect complexity increases
Solution Approach 1:
The patent applies different interconnect configurations to different regions of the seal ring. Specifically, redistribution layers and vias are excluded from corner regions where stress concentration occurs, while maintaining full interconnect functionality in straight sections. This local differentiation reduces cracking and delamination risk at critical corners without unnecessarily complicating the overall interconnect structure.
Data Source
AI summary
A semiconductor structure that includes a substrate having a circuit region and a seal ring region around the circuit region. The seal ring region includes a multi-layer interconnect to form a seal ring structure. And a redistribution layer is formed over the seal ring structure. The redistribution layer is formed on the edges of the seal ring region, and excluded from corner regions of the seal ring.