Semiconductor Seal Ring Structure for GAA Moisture Isolation
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Solution Overview
Problem
Existing seal ring structures in semiconductor technologies are not adequately compatible with the fabrication processes for gate-all-around (GAA) transistors, particularly for nanosheet devices, which require improved protection against moisture degradation and ionic contamination.
Innovation Solution
The proposed solution involves forming a seal ring with stacked semiconductor layers and sacrificial gate structures, where the poly gates are removed, and the semiconductor layers in the seal ring undergo no channel release process, while those in the circuit die area do. This results in a stable and robust seal ring wall, compatible with GAA transistor fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing seal ring structures are used, then fabrication processes are simpler, but compatibility with GAA transistor fabrication is insufficient and protection against moisture degradation is inadequate
Solution Approach 1:
The seal ring structure is segmented into multiple functional layers including a first seal ring layer, second seal ring layer, and third seal ring layer, each performing specific protective functions. This segmentation allows the structure to provide enhanced protection against moisture degradation while maintaining compatibility with GAA transistor fabrication processes through modular design
Solution Approach 2:
Different regions of the seal ring structure are assigned different properties and functions. The first seal ring layer provides base protection, the second layer adds intermediate protection, and the third layer provides enhanced protection. This local differentiation of quality allows the structure to achieve superior overall reliability without requiring uniform complexity throughout
2Object-affected harmful factors
If seal rings are formed during FEOL and BEOL processing, then circuits are protected from moisture and ionic contamination, but the seal ring structure becomes complex and compatibility with GAA devices is reduced
Solution Approach 1:
The first seal ring layer is formed during FEOL processing before the GAA transistor structures are fully developed. This preliminary action establishes a protective base layer that will accommodate subsequent GAA transistor fabrication steps without interfering with the formation of nanosheet channels and gate structures
Solution Approach 2:
The seal ring structure is nested within the GAA transistor fabrication sequence, with the first seal ring layer formed during FEOL, the second layer formed during intermediate processing, and the third layer formed during BEOL. Each layer is nested within the structural framework established by previous layers, allowing compatibility with GAA processes while building comprehensive protection against ionic contamination
Data Source
AI summary
A method includes providing a structure having a substrate and first and second semiconductor layers alternately stacked one over another above the substrate, etching the first and the second semiconductor layers to form a first continuous ring in a seal ring region of the structure, and forming an isolation structure adjacent the first continuous ring in the seal ring region. The method further includes forming a dummy gate structure that is disposed directly above the first continuous ring and completely within a boundary of the first continuous ring from a top view, growing first and second epitaxial features sandwiching the dummy gate structure, removing the dummy gate structure, resulting in a gate trench that exposes a topmost layer of the first semiconductor layers and does not expose side surfaces of the first and second semiconductor layers, and depositing a gate structure in the gate trench.