Seal Ring Structure with Hollow Through-Holes for Semiconductor Delamination Prevention

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Solution Overview

Problem

Conventional semiconductor manufacturing methods fail to prevent delamination defects in semiconductor devices during laser scribing and cutting processes, especially at technology nodes below 40 nm, due to stress-induced cracking and peeling, which affects the functional integrity and yield of the chips.

Innovation Solution

A semiconductor device with a seal ring structure comprising interlayer dielectric layers and hollow through-hole structures, where a diffusion barrier layer and a seed layer are sequentially formed within the through-holes to buffer stress, using materials like tantalum, titanium, or copper, and having a critical dimension less than 45 nm, to reduce stress and prevent delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional laser scribing and cutting processes are used, then manufacturing efficiency is maintained, but delamination and cracking defects occur due to stress concentration

Engineering Contradiction:

Improvemanufacturing efficiencyVSAvoiddefect-free yield

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies beforehand cushioning by forming a seal ring structure with hollow through-hole filled with stress-buffering material (such as tungsten, copper, or other metals) in the interlayer dielectric layer before the laser scribing and cutting processes. This pre-installed stress buffer absorbs and distributes the stress generated during subsequent cutting operations, preventing stress concentration that would otherwise cause delamination and cracking defects, thus maintaining both manufacturing efficiency and defect-free yield

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Object-affected harmful factors

If the size of test pad and copper metal layer in scribe line is reduced, then stress from laser cutting is minimized, but delamination prevention is insufficient

Engineering Contradiction:

Improvelaser cutting stressVSAvoiddelamination resistance

Core Design Contradiction:

Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent introduces an intermediary element - the seal ring structure with hollow through-hole filled with stress-buffering material - that acts as a mediator between the laser cutting process and the chip structure. This intermediary absorbs and distributes the stress generated during laser scribing and cutting, transforming the harmful stress into manageable forces that do not cause delamination, thereby providing superior delamination resistance compared to simply reducing the size of test pads and copper metal layers

Inventive Principle:

Principle #24Intermediary (Mediator)

3Adaptability or versatility

If low dielectric constant materials are used, then next-generation semiconductor process requirements are met, but fracture toughness and adhesion between layers are greatly reduced

Engineering Contradiction:

Improvecompatibility with next-generation processesVSAvoidinterlayer adhesion

Core Design Contradiction:

Adaptability or versatilityVSStrength

Solution Approach 1:

Inventive Principle:

Principle #24Intermediary (Mediator)

4Shape

If conventional seal ring structures are used, then chip edge sealing is provided, but stress-induced delamination cannot be prevented

Engineering Contradiction:

Improveseal ring structureVSAvoiddelamination prevention

Core Design Contradiction:

ShapeVSReliability

Solution Approach 1:

The patent applies local quality by modifying the seal ring structure with a hollow through-hole filled with stress-buffering material at the specific location where stress concentration occurs during laser scribing and cutting. This localized modification creates a stress buffer zone exactly where needed, providing delamination prevention capability that conventional uniform seal ring structures cannot achieve

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS10249574B2Method for manufacturing a seal ring structure to avoid delamination defect

Publication Date: 2019.04.02 SEMICON MFG INT (SHANGHAI) CORP

AI summary

A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a plurality of integrated circuit (IC) devices on the semiconductor substrate, and forming a seal ring structure surrounding each of the IC devices. Forming the seal ring structure includes forming a plurality of interlayer dielectric layers on the semiconductor substrate, and forming a plurality of hollow through-hole structures within each of the interlayer dielectric layers.