Semiconductor Seal Ring Noise Shielding
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Solution Overview
Problem
Existing semiconductor device fabrication methods result in seal ring structures that degrade the electrical performance of semiconductor devices due to noise signal interference and moisture ingress, which are not effectively addressed by current shielding and protection mechanisms.
Innovation Solution
A method involving the formation of a buried deep-well layer with a different doping type, surrounded by well regions and a heavily doped region, which forms an anti-jamming barrier to isolate the substrate from noise signals and moisture, using specific ion implantation processes and patterned layers to create a seal ring structure connected to the heavily doped region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a seal ring structure is formed using existing fabrication methods, then the chip is protected from dicing damage, but the electrical performance of the semiconductor device degrades due to noise signal interference
Solution Approach 1:
The seal ring structure is divided into multiple segments: a first seal ring structure and a second seal ring structure separated by a first gap, with additional segmentation through contact hole plugs and metal interconnection layers. This segmented approach allows the seal ring to provide mechanical protection while reducing continuous noise signal pathways that would degrade electrical performance.
Solution Approach 2:
Interlayer dielectric layers are introduced as intermediary materials between the seal ring structures and the substrate/device areas. These dielectric layers act as mediators that electrically isolate the seal ring from sensitive device regions while maintaining the mechanical protection function, thereby reducing noise signal interference.
2Reliability
If a seal ring structure is formed using existing fabrication methods, then the chip is protected from dicing damage, but moisture can still enter the chip through fracture surfaces on the edges
Solution Approach 1:
The seal ring structure implements a nested configuration where the first seal ring structure surrounds the device area, and the second seal ring structure surrounds the first seal ring structure with a second gap. This nested arrangement creates multiple concentric barriers that collectively prevent moisture from reaching the chip edges through fracture surfaces, while the segmented design maintains electrical performance.
3Reliability
If the seal ring structure is positioned closer to the chip for better protection, then dicing protection is improved, but noise signal shielding effectiveness decreases
Solution Approach 1:
The seal ring structure is extended into the vertical dimension with multiple layers at different heights. The first and second seal ring structures are positioned at different vertical levels, connected through contact hole plugs and metal interconnection layers. This three-dimensional configuration allows the seal ring to provide mechanical protection close to the chip while maintaining noise shielding effectiveness through vertical separation and multiple shielding planes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses noise signal interference and prevents moisture ingress, thereby enhancing the electrical performance and protection of semiconductor devices during the dicing process and operation.
Implementation Method 1
forming a buried deep-well layer in the substrate of the seal ring area to surround the device area. The buried deep-well layer has a first doping type different from a second doping type of the substrate. Each of the first well region and the second well region has the first doping type
Implementation Method 2
The buried deep-well layer may be formed by a first ion implantation process performed on the substrate of the seal ring area with process parameters including: implanting ions, including phosphor ions, arsenic ions, and antimony ions
Data Source
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AI summary
A semiconductor device and a fabrication method are provided. The semiconductor device is fabricated by providing a substrate with a device area surrounded by a seal ring area, forming a buried deep-well layer in the substrate of the seal ring area, forming a first well region and a second well region in the substrate above the buried deep-well layer with the first well region surrounding the device area and the second well region surrounding the first well region, forming a heavily doped region in the substrate above the buried deep-well layer and between the first well region and the second well region, and forming a seal ring structure connecting to the heavily doped region. The buried deep-well layer, the first well region, and the second well region all have a first doping type while the heavily doped region and the substrate have a second doping type.