Sealant Material Caps Voids to Reduce Parasitic Capacitance
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Solution Overview
Problem
Parasitic capacitance between interconnects and digit lines in DRAM cells is a problem that existing technologies have not adequately addressed, and sealing void regions to prevent this capacitance is challenging.
Innovation Solution
A method involving the formation of sealant material across openings to trap voids, where particles are sputtered from a mass deposited on conductive structures to form a low-permittivity sealant that caps voids along sidewalls, reducing parasitic capacitance by creating low-k regions between conductive structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If void regions are used as low-k regions between conductive structures, then parasitic capacitance is reduced, but sealing the void regions becomes problematic
Solution Approach 1:
The patent applies preliminary action by forming a sealant material around the void region before finalizing the conductive structure assembly. The sealant material is deposited to surround the void region, creating a sealed environment that prevents contamination while maintaining the low-k properties. This preliminary sealing action resolves the contradiction by enabling void region usage without compromising manufacturability.
Solution Approach 2:
The sealant material acts as an intermediary between the void region and the external environment. It provides a protective barrier that allows the void region to function as a low-k region while preventing contamination and maintaining structural integrity. This intermediary solution enables both the reduction of parasitic capacitance and the ease of manufacturing by sealing the void regions effectively.
2Productivity
If interconnects are placed proximate to digit lines, then device density is improved, but parasitic capacitance between interconnects and digit lines increases
Solution Approach 1:
The patent applies local quality by creating a localized low-k environment around specific interconnects that are proximate to digit lines. The void regions filled with sealant material are selectively formed only where needed to reduce parasitic capacitance between interconnects and digit lines, while maintaining high device density. This localized approach resolves the contradiction by providing capacitance reduction only where harmful interactions occur.
Solution Approach 2:
The patent utilizes porous materials by incorporating void regions that are subsequently sealed with sealant material. The void regions create a low-k environment that reduces parasitic capacitance between proximate interconnects and digit lines, while the sealant material maintains the structural integrity and prevents contamination. This approach enables high device density without suffering from excessive parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance by creating low-k regions, improving the architecture of integrated assemblies and preventing capacitance issues between digit lines and interconnects, enhancing the performance of memory arrays like DRAM.
Implementation Method 1
particles are sputtered from the mass deposited on conductive structures to form a low-permittivity sealant
Data Source
AI summary
Some embodiments include a method of forming an integrated assembly. A construction is formed to include a structure having an exposed surface, and to include an opening proximate the structure. An aperture extends into the opening. A first material is deposited to form a mass along the exposed surface of the structure. Particles are sputtered from the mass and across the aperture. The particles agglomerate to form a sealant material which traps a void within the opening.