Sealed Air Gap for Semiconductor Gate Sidewalls
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Solution Overview
Problem
Semiconductor chips face increased power consumption and reduced performance due to high parasitic capacitances caused by silicon nitride spacers adjacent to gate sidewalls, while oxide spacers are not robust enough for middle-of-line processing.
Innovation Solution
Forming sealed air gaps between the gate sidewalls, dielectric layers, and contacts by removing sacrificial spacers and depositing a second dielectric layer over the first dielectric layer, which reduces parasitic capacitance and enhances processing robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nitride spacers are formed adjacent to gate sidewalls, then structural robustness is improved, but parasitic capacitance increases leading to higher power consumption
Solution Approach 1:
The patent removes the silicon nitride spacer material adjacent to the gate sidewall, extracting the harmful high-dielectric-constant material that causes parasitic capacitance. This is achieved through selective etching processes that remove the spacer while preserving the gate structure and forming the desired air gap region.
Solution Approach 2:
The patent introduces air gaps (porous regions) adjacent to the gate sidewall by removing the solid spacer material. These air gaps provide the lowest possible dielectric constant, minimizing parasitic capacitance while maintaining structural integrity through the surrounding dielectric layers and contact structures.
2Loss of energy
If oxide spacers are used instead of nitride spacers, then parasitic capacitance is reduced, but processing robustness deteriorates
Solution Approach 1:
The patent uses a sacrificial spacer (typically silicon nitride) as an intermediary material during fabrication. This sacrificial spacer is easily removed through selective etching to create the air gap structure. The intermediary approach allows precise control of the air gap formation while maintaining processing robustness through well-established etching chemistry.
Solution Approach 2:
The patent changes the material parameter of the spacer from oxide (which has processing issues) to a sacrificial nitride material that can be selectively removed. This parameter change enables the formation of air gaps with controlled dimensions and positioning, achieving both low parasitic capacitance and processing robustness.
3Loss of energy
If air gaps are formed adjacent to gate sidewalls, then parasitic capacitance is minimized, but manufacturing complexity increases
Solution Approach 1:
The patent forms the sacrificial spacer adjacent to the gate sidewall before contact formation and other middle-of-line processing steps. This preliminary placement of the spacer defines the future air gap region and protects the gate sidewall during subsequent processing, simplifying the overall manufacturing sequence.
Solution Approach 2:
The sacrificial spacer self-aligns to the gate sidewall through conformal deposition, automatically defining the air gap position and dimension without requiring additional alignment steps. The selective etching process then self-selectively removes only the spacer material, leaving the gate and surrounding structures intact, thereby reducing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes parasitic capacitance and improves the robustness of semiconductor chip components, leading to more efficient operation and reduced power consumption.
Implementation Method 1
substantially removing the sacrificial spacer, wherein a space is formed between the gate and the first dielectric layer
Implementation Method 2
forming a sealed air gap in the space by depositing a second dielectric layer over the first dielectric layer
Data Source
AI summary
A method for forming a sealed air gap for a semiconductor chip including forming a gate over a substrate; forming a sacrificial spacer adjacent to the gate; forming a first dielectric layer about the gate and the sacrificial spacer; forming a contact to the gate; substantially removing the sacrificial spacer, wherein a space is formed between the gate and the first dielectric layer; and forming a sealed air gap in the space by depositing a second dielectric layer over the first dielectric layer.