DRAM Bit Line Air Gap Layout for Reduced Capacitive Coupling
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Solution Overview
Problem
The reduction in size of dynamic random-access memory (DRAM) cells leads to increased parasitic capacitance, which reduces the speed of DRAM memory cells and negatively affects overall device performance due to capacitive coupling.
Innovation Solution
A semiconductor structure is manufactured with a method that includes forming bit lines on a substrate, creating a patterned layer and a conformal layer, forming a contact taller than the patterned layer, and removing the layers to form an air gap sealed by a dielectric layer, which reduces parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of DRAM memory cells is reduced to increase packaging density, then the packaging density increases, but the parasitic capacitance increases due to capacitive coupling
Solution Approach 1:
The patent extracts the harmful dielectric material between adjacent bit lines and replaces it with air, creating air gaps that eliminate parasitic capacitance. This is achieved by forming air gaps between the first and second bit lines, effectively removing the source of capacitive coupling while maintaining the high-density cell structure
Solution Approach 2:
The patent applies different dielectric properties to different regions: air (vacuum) is used between adjacent bit lines to minimize capacitance, while solid dielectric materials are used elsewhere for electrical insulation and structural support. This localized differentiation of material properties optimizes the trade-off between density and performance
2Area of stationary object
If the size of DRAM memory cells is reduced, then the packaging density increases, but the speed of DRAM memory cells decreases due to increased parasitic capacitance
Solution Approach 1:
By removing the dielectric material between bit lines and replacing it with air gaps, the patent eliminates parasitic capacitance that would otherwise slow down signal transitions. This extraction of harmful material directly improves the speed of memory cell operations while maintaining high density
3Object-generated harmful factors
If air gaps are formed between bit lines to reduce parasitic capacitance, then the parasitic capacitance decreases, but the device structure becomes more complex
Solution Approach 1:
The patent incorporates air gap formation into the existing bit line fabrication sequence, creating air gaps during the same processing steps used to form the bit lines themselves. This preliminary integration avoids the need for separate air gap formation steps and maintains manufacturing simplicity
Solution Approach 2:
The air gap structure serves multiple functions: it reduces parasitic capacitance between bit lines, provides electrical isolation, and maintains the mechanical integrity of the device. This multi-functionality justifies the additional structural element without proportionally increasing complexity
Data Source
AI summary
The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a first bit line on a substrate; a contact adjacent to the first bit line on the substrate, wherein a first distance between a top portion of the contact and the first bit line is less than a second distance between a lower portion of the contact and the first bit line; a dielectric layer, disposed conformally over the first bit line, the substrate, and the contact; and a first air gap, sealed by the dielectric layer and defined by the first bit line, the substrate and the contact.