Transistor Isolation Spacers With Sealed Air Gaps for GAA FETs
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Solution Overview
Problem
Gate-all-around (GAA) field effect transistors (FETs) face parasitic capacitance issues due to the formation of parasitic capacitors between the metal gate structure, spacer structure, and source/drain epitaxial structures, which can hinder their operation, particularly when the spacer material has a high dielectric constant.
Innovation Solution
The use of a low dielectric constant spacer material with a dielectric constant between 3.7 and 5.2, incorporating air gaps or cavities, and a silicon nitride-based material with tunable nitrogen and oxygen concentrations, deposited using thermal atomic layer deposition and treated with post-deposition processes, is employed to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high dielectric constant spacer material is used, then the spacer structure provides good electrical isolation, but parasitic capacitance increases and hinders transistor operation
Solution Approach 1:
The patent changes the dielectric constant parameter of the spacer material from high to low (between 3.7 and 5.2) to reduce parasitic capacitance. This parameter change directly addresses the contradiction by selecting materials with lower dielectric constants while maintaining adequate electrical isolation functionality.
Solution Approach 2:
The patent employs composite spacer structures combining silicon nitride-based material with air gaps or cavities. This composite approach reduces the effective dielectric constant of the spacer structure while maintaining mechanical integrity and electrical isolation, thereby reducing parasitic capacitance between the gate and source/drain regions.
2Object-affected harmful factors
If the dielectric constant of spacer material is reduced to mitigate parasitic capacitance, then parasitic capacitance decreases, but the electrical isolation capability may be compromised
Solution Approach 1:
The patent uses composite spacer structures combining silicon nitride-based material with air gaps or cavities. The silicon nitride provides baseline electrical isolation while the air gaps (with dielectric constant接近1) reduce the overall effective dielectric constant. This composite approach maintains adequate electrical isolation while significantly reducing parasitic capacitance.
Solution Approach 2:
The patent introduces air gaps or cavities at specific locations within the spacer structure, creating local regions of low dielectric constant. This local quality change reduces parasitic capacitance in critical areas while maintaining the overall spacer structure's electrical isolation functionality through the remaining solid material portions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates parasitic capacitances by reducing the dielectric constant of the spacer material, improving the operational efficiency of GAA FETs by minimizing electrical interference and enhancing performance.
Implementation Method 1
The use of a low dielectric constant spacer material with a dielectric constant between 3.7 and 5.2... effectively mitigates parasitic capacitances by reducing the dielectric constant of the spacer material
Implementation Method 2
deposited using thermal atomic layer deposition
Data Source
AI summary
The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.