Sealed Semiconductor Chip Layout to Prevent Bonding Wire Drop
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Solution Overview
Problem
In packaged semiconductor devices with a thin small outline package (TSOP) structure, long bonding wires are required to connect internal leads to pads, leading to issues with wire drop and electrical short-circuiting during resin sealing, due to the close arrangement of internal leads and pads.
Innovation Solution
A semiconductor device design featuring a lead frame with varying internal lead lengths, where shorter leads are connected to pads using first bonding wires and longer leads are connected using second bonding wires, with a hanging pin section and organic insulation film to stabilize the chip and prevent wire length issues, and a sealing member that includes the hanging pin section and bonding wires to enhance moldability and reduce wire length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If internal leads are arranged close to pads to reduce chip size, then chip area is reduced, but bonding wire length increases causing wire drop and electrical short-circuiting
Solution Approach 1:
The patent segments the internal leads into two distinct groups: first internal leads arranged close to pads for short bonding wires, and second internal leads arranged away from pads for long bonding wires. This segmentation allows each group to be optimized independently, resolving the contradiction between compact layout and wire reliability.
Solution Approach 2:
Different regions of the chip are assigned different lead arrangements: the first internal leads are positioned in regions where short bonding wires are needed (close to pads), while second internal leads are positioned in regions where long bonding wires are acceptable (away from pads). This local differentiation optimizes both area utilization and wire reliability.
2Ease of manufacture
If very long bonding wires are used to connect distant internal leads to pads, then all internal leads can be connected, but wire drop and electrical short-circuiting occur during resin sealing
Solution Approach 1:
The patent divides internal leads into two segments with different connectivity requirements. First internal leads are connected to nearby pads with short wires for stability, while second internal leads are connected to distant pads with long wires only where necessary, reducing the overall number of long vulnerable wires.
Solution Approach 2:
The patent introduces a protective structure (mold compound and optional support elements) that acts as an intermediary between the bonding wires and the external environment, preventing wire drop and short-circuiting during resin sealing while maintaining electrical connectivity.
Data Source
AI summary
A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding vires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.