Semiconductor Package Sealing Ring Interconnects for Direct Die Stacking

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Solution Overview

Problem

As the semiconductor industry continues to increase integration density by reducing minimum feature sizes, connecting integrated circuit dies through interposers alone becomes challenging due to increased complexity and density.

Innovation Solution

The implementation of integrated circuit dies with vertical interconnect features, which are segments of a sealing ring formed in the seal region, allowing direct connection with another integrated circuit die stacked on top without the need for an interposer, combined with edge interconnect features for additional connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If interposers are used to connect integrated circuit dies, then connectivity between dies is achieved, but device complexity and manufacturing difficulty increase due to increased integration density

Engineering Contradiction:
Improveconnectivity between diesVSAvoidcomplexity of interposer structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the interposer component from the system by implementing direct die-to-die bonding. The sealing ring structure is modified to include conductive portions that enable direct electrical connection between stacked dies, removing the intermediate interposer layer that previously provided connectivity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the sealing function and the electrical connection function into a single integrated structure. The sealing ring is combined with conductive interconnect features to create a multi-functional component that provides both environmental sealing and electrical connectivity between dies without requiring separate interposer structures.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If interposers are used for connecting integrated circuit dies, then electrical connection is established, but manufacturing cost and process complexity increase due to redistribution requirements

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidmanufacturing process simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent removes the interposer and associated redistribution layer processes from the manufacturing workflow. Direct die stacking with conductive sealing ring interconnects eliminates the need for complex interposer fabrication, patterning, and assembly steps, significantly simplifying the manufacturing process.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The conductive interconnect features are formed as integral parts of the die structure during the semiconductor fabrication process, before the dies are stacked. This preliminary formation of connection structures eliminates the need for post-assembly redistribution operations and simplifies the overall manufacturing flow.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If integration density is increased by reducing minimum feature size, then more components are integrated into a given area, but connecting dies through interposers becomes more challenging

Engineering Contradiction:
Improveintegration densityVSAvoiddifficulty of die connection
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent transitions from planar interconnection through interposers to three-dimensional direct stacking of dies. By utilizing vertical stacking with conductive sealing ring interconnects, the system achieves higher integration density without proportionally increasing connection complexity, as the connection path becomes more direct in the vertical dimension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12211799B2Semiconductor packages and methods for forming the same
Publication Date: 2025.01.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12211799B2 patent drawing
  • US12211799B2 patent drawing
  • US12211799B2 patent drawing

AI summary

Embodiments of the present disclosure provide an integrated circuit die with vertical interconnect features to enable direct connection between vertically stacked integrated circuit dies. The vertical interconnect features may be formed in a sealing ring, which allows higher routing density than interposers or redistribution layer. The direct connection between vertically stacked integrated circuit dies reduces interposer layers, redistribution process, and bumping processes in multi-die integration, thus, reducing cost of manufacturing.